mirror of
https://github.com/cesanta/mongoose.git
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82 lines
3.2 KiB
Plaintext
82 lines
3.2 KiB
Plaintext
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This is a FreeeRTOS+TCP driver that works for both STM32F4xx and STM32F7xx parts.
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The code of stm32fxx_hal_eth.c is based on both drivers as provided by ST.
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These modules should be included:
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NetworkInterface.c
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stm32fxx_hal_eth.c
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It is assumed that one of these words are defined:
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STM32F7xx
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STM32F407xx
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STM32F417xx
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STM32F427xx
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STM32F437xx
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STM32F429xx
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STM32F439xx
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The driver has been tested on both Eval and Discovery boards with both STM32F4 and STM32F7.
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Recommended settings for STM32Fxx Network Interface:
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// Defined in FreeRTOSIPConfig.h
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#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 1
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#define ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM 1
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#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1
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#define ipconfigZERO_COPY_RX_DRIVER 1
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#define ipconfigZERO_COPY_TX_DRIVER 1
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#define ipconfigUSE_LINKED_RX_MESSAGES 1
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// Defined in stm32f4xx_hal_conf.h
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#define ETH_RXBUFNB 3 or 4
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#define ETH_TXBUFNB 2 or 3
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#define ETH_RX_BUF_SIZE ( ipconfigNETWORK_MTU + 36 )
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#define ETH_TX_BUF_SIZE ( ipconfigNETWORK_MTU + 36 )
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The best size for 'ETH_RXBUFNB' and 'ETH_TXBUFNB' depends on the speed of the CPU. These macro's define the number of DMA buffers for reception and for transmission.
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In general, if the CPU is very fast, you will need less buffers. You can obtain an estimate empirically.
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The optimal value of 'ETH_RX_BUF_SIZE' and 'ETH_TX_BUF_SIZE' depends on the actual value of 'ipconfigNETWORK_MTU'.
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When MTU is 1500, MTU+36 becomes a well-aligned buffer of 1536 bytes ( 0x600 ).
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When MTU is 1200, MTU+48 will make 1248 ( 0x4E0 ), which is also well aligned.
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Having well aligned buffers is important for CPU with memory cache. Often the caching system divides memory in blocks of 32 bytes. When two buffers share the same cache buffer, you are bound to see data errors.
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Without memory caching, let the size be at least a multiple of 8 ( for DMA ), and make it at least "ipconfigNETWORK_MTU + 14".
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STM32F7xx only:
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Networkinterface.c will place the 2 DMA tables in a special section called 'first_data'.
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In case 'BufferAllocation_1.c' is used, the network packets will also be declared in this section 'first_data'.
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As long as the part has no caching, this section can be placed anywhere in RAM.
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On an STM32F7 with an L1 data cache, it shall be placed in the first 64KB of RAM, which is always uncached.
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The linker script must be changed for this, for instance as follows:
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.data :
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{
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. = ALIGN(4);
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_sdata = .; // create a global symbol at data start
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+ *(.first_data) // .first_data sections
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*(.data) // .data sections
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*(.data*) // .data* sections
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. = ALIGN(4);
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_edata = .; // define a global symbol at data end
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} >RAM AT> FLASH
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The driver contains these files:
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stm32fxx_hal_eth.c
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stm32f2xx_hal_eth.h
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stm32f4xx_hal_eth.h
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stm32f7xx_hal_eth.h
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stm32fxx_hal_eth.h
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These files are copied from ST's HAL library. These work both for STM32F4 and STM32F7.
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Please remove or rename these files from the HAL distribution that you are using.
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