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54 lines
2.0 KiB
C
54 lines
2.0 KiB
C
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// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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//
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// This file contains essentials required by the CMSIS:
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// uint32_t SystemCoreClock - holds the system core clock value
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// SystemInit() - initialises the system, e.g. sets up clocks
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#include "hal.h"
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uint32_t SystemCoreClock = CPU_FREQUENCY;
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static inline unsigned int div2prescval(unsigned int div) {
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// 0 --> /1; 8 --> /2 ... 11 --> /16; 12 --> /64 ... 15 --> /512
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if (div == 1) return 0;
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if (div > 16) div /= 2;
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unsigned int val = 7;
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while (div >>= 1) ++val;
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return val;
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}
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static inline unsigned int pllrge(unsigned int f) {
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unsigned int val = 0;
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while (f >>= 1) ++val;
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return val - 1;
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}
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void SystemInit(void) { // Called automatically by startup code
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
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__DSB();
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__ISB();
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// Set flash latency. RM0481, section 7.11.1, section 7.3.4 table 37
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SETBITS(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
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FLASH_ACR_LATENCY_7WS | FLASH_ACR_WRHIGHFREQ_1);
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SETBITS(
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RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),
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(div2prescval(D1CPRE) << 8) | (D1PPRE << 4) | (div2prescval(HPRE) << 0));
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RCC->D2CFGR = (D2PPRE2 << 8) | (D2PPRE1 << 4);
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RCC->D3CFGR = (D3PPRE << 4);
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SETBITS(RCC->PLLCFGR, 3 << 2,
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pllrge(PLL1_HSI / PLL1_M)
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<< 2); // keep reset config (DIVP1EN, !PLL1VCOSEL), PLL1RGE
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SETBITS(RCC->PLL1DIVR, (0x7F << 9) | (0x1FF << 0),
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((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0)); // Set PLL1_P PLL1_N
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SETBITS(RCC->PLLCKSELR, 0x3F << 4,
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PLL1_M << 4); // Set PLL1_M (source defaults to HSI)
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RCC->CR |= BIT(24); // Enable PLL1
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while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done
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RCC->CFGR |= (3 << 0); // Set clock source to PLL1
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while ((RCC->CFGR & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
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RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; // Enable SYSCFG
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rng_init();
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SysTick_Config(CPU_FREQUENCY / 1000);
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}
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