mirror of
https://github.com/cesanta/mongoose.git
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262 lines
13 KiB
C
262 lines
13 KiB
C
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/*
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* Copyright 2022, NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_RESET_H_
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#define _FSL_RESET_H_
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "fsl_device_registers.h"
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/*!
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* @addtogroup reset
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief reset driver version 2.4.0 */
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#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
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/*@}*/
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/*!
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* @brief Enumeration for peripheral reset control bits
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*
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* Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
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*/
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typedef enum _SYSCON_RSTn
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{
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kFMU_RST_SHIFT_RSTn = 0 | 9U, /**< Flash management unit reset control */
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kFLEXSPI_RST_SHIFT_RSTn = 0 | 11U, /**< FLEXSPI reset control */
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kMUX_RST_SHIFT_RSTn = 0 | 12U, /**< Input mux reset control */
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kPORT0_RST_SHIFT_RSTn = 0 | 13U, /**< PORT0 reset control */
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kPORT1_RST_SHIFT_RSTn = 0 | 14U, /**< PORT1 reset control */
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kPORT2_RST_SHIFT_RSTn = 0 | 15U, /**< PORT2 reset control */
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kPORT3_RST_SHIFT_RSTn = 0 | 16U, /**< PORT3 reset control */
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kPORT4_RST_SHIFT_RSTn = 0 | 17U, /**< PORT4 reset control */
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kGPIO0_RST_SHIFT_RSTn = 0 | 19U, /**< GPIO0 reset control */
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kGPIO1_RST_SHIFT_RSTn = 0 | 20U, /**< GPIO1 reset control */
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kGPIO2_RST_SHIFT_RSTn = 0 | 21U, /**< GPIO2 reset control */
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kGPIO3_RST_SHIFT_RSTn = 0 | 22U, /**< GPIO3 reset control */
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kGPIO4_RST_SHIFT_RSTn = 0 | 23U, /**< GPIO4 reset control */
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kPINT_RST_SHIFT_RSTn = 0 | 25U, /**< Pin interrupt (PINT) reset control */
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kDMA0_RST_SHIFT_RSTn = 0 | 26U, /**< DMA0 reset control */
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kCRC_RST_SHIFT_RSTn = 0 | 27U, /**< CRC reset control */
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kMAILBOX_RST_SHIFT_RSTn = 0 | 31U, /**< Mailbox reset control */
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kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
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kOSTIMER_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer reset control */
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kSCT_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM(SCT) reset control */
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kADC0_RST_SHIFT_RSTn = 65536 | 3U, /**< ADC0 reset control */
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kADC1_RST_SHIFT_RSTn = 65536 | 4U, /**< ADC1 reset control */
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kDAC0_RST_SHIFT_RSTn = 65536 | 5U, /**< DAC0 reset control */
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kEVSIM0_RST_SHIFT_RSTn = 65536 | 8U, /**< EVSIM0 reset control */
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kEVSIM1_RST_SHIFT_RSTn = 65536 | 9U, /**< EVSIM1 reset control */
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kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
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kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
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kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
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kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
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kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
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kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
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kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
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kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
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kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
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kFC8_RST_SHIFT_RSTn = 65536 | 19U, /**< Flexcomm Interface 8 reset control */
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kFC9_RST_SHIFT_RSTn = 65536 | 20U, /**< MICFIL reset control */
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kMICFIL_RST_SHIFT_RSTn = 65536 | 21U, /**< Flexcomm Interface 7 reset control */
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kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */
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kUSB0_RAM_RST_SHIFT_RSTn = 65536 | 23U, /**< USB0 RAM reset control */
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kUSB0_FS_DCD_RST_SHIFT_RSTn = 65536 | 24U, /**< USB0-FS DCD reset control */
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kUSB0_FS_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0-FS reset control */
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kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */
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kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */
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kSMART_DMA_RST_SHIFT_RSTn = 65536 | 31U, /**< SmartDMA reset control */
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kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */
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kENET_RST_SHIFT_RSTn = 131072 | 2U, /**< Ethernet reset control */
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kUSDHC_RST_SHIFT_RSTn = 131072 | 3U, /**< uSDHC reset control */
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kFLEXIO_RST_SHIFT_RSTn = 131072 | 4U, /**< FLEXIO reset control */
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kSAI0_RST_SHIFT_RSTn = 131072 | 5U, /**< SAI0 reset control */
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kSAI1_RST_SHIFT_RSTn = 131072 | 6U, /**< SAI1 reset control */
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kTRO_RST_SHIFT_RSTn = 131072 | 7U, /**< TRO reset control */
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kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */
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kTRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< TRNG reset control */
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kFLEXCAN0_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcan0 reset control */
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kFLEXCAN1_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcan1 reset control */
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kUSB_HS_RST_SHIFT_RSTn = 131072 | 16U, /**< USB HS reset control */
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kUSB_HS_PHY_RST_SHIFT_RSTn = 131072 | 17U, /**< USB HS PHY reset control */
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kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */
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kPLU_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU reset control */
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kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */
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kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */
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kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */
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kPKC_RST_SHIFT_RSTn = 131072 | 24U, /**< PKC reset control */
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kSM3_RST_SHIFT_RSTn = 131072 | 30U, /**< SM3 reset control */
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kI3C0_RST_SHIFT_RSTn = 196608 | 0U, /**< I3C0 reset control */
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kI3C1_RST_SHIFT_RSTn = 196608 | 1U, /**< I3C1 reset control */
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kSINC_RST_SHIFT_RSTn = 196608 | 2U, /**< SINC reset control */
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kCOOLFLUX_RST_SHIFT_RSTn = 196608 | 3U, /**< CoolFlux reset control */
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kENC0_RST_SHIFT_RSTn = 196608 | 4U, /**< ENC0 reset control */
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kENC1_RST_SHIFT_RSTn = 196608 | 5U, /**< ENC1 reset control */
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kPWM0_RST_SHIFT_RSTn = 196608 | 6U, /**< PWM0 reset control */
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kPWM1_RST_SHIFT_RSTn = 196608 | 7U, /**< PWM1 reset control */
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kAOI0_RST_SHIFT_RSTn = 196608 | 8U, /**< AOI0 reset control */
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kDAC1_RST_SHIFT_RSTn = 196608 | 11U, /**< DAC1 reset control */
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kDAC2_RST_SHIFT_RSTn = 196608 | 12U, /**< DAC2 reset control */
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kOPAMP0_RST_SHIFT_RSTn = 196608 | 13U, /**< OPAMP0 reset control */
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kOPAMP1_RST_SHIFT_RSTn = 196608 | 14U, /**< OPAMP1 reset control */
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kOPAMP2_RST_SHIFT_RSTn = 196608 | 15U, /**< OPAMP2 reset control */
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kCMP2_RST_SHIFT_RSTn = 196608 | 18U, /**< CMP2 reset control */
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kVREF_RST_SHIFT_RSTn = 196608 | 19U, /**< VREF reset control */
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kCOOLFLUX_APB_RST_SHIFT_RSTn = 196608 | 20U, /**< CoolFlux APB reset control */
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kNEUTRON_RST_SHIFT_RSTn = 196608 | 21U, /**< Neutron mini reset control */
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kTSI_RST_SHIFT_RSTn = 196608 | 22U, /**< TSI reset control */
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kEWM_RST_SHIFT_RSTn = 196608 | 23U, /**< EWM reset control */
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kEIM_RST_SHIFT_RSTn = 196608 | 24U, /**< EIM reset control */
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kSEMA42_RST_SHIFT_RSTn = 196608 | 27U, /**< Semaphore reset control */
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} SYSCON_RSTn_t;
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/** Array initializers with peripheral reset bits **/
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#define ADC_RSTS \
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{ \
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kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \
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} /* Reset bits for ADC peripheral */
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#define CRC_RSTS \
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{ \
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kCRC_RST_SHIFT_RSTn \
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} /* Reset bits for CRC peripheral */
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#define CTIMER_RSTS \
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{ \
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kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
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kCTIMER4_RST_SHIFT_RSTn \
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} /* Reset bits for CTIMER peripheral */
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#define DMA_RSTS_N \
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{ \
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kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
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} /* Reset bits for DMA peripheral */
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#define LP_FLEXCOMM_RSTS \
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{ \
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kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
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kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn \
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} /* Reset bits for FLEXCOMM peripheral */
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#define GPIO_RSTS_N \
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{ \
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kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \
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kGPIO4_RST_SHIFT_RSTn \
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} /* Reset bits for GPIO peripheral */
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#define INPUTMUX_RSTS \
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{ \
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kMUX_RST_SHIFT_RSTn \
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} /* Reset bits for INPUTMUX peripheral */
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#define FLASH_RSTS \
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{ \
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kFMC_RST_SHIFT_RSTn \
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} /* Reset bits for Flash peripheral */
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#define MRT_RSTS \
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{ \
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kMRT_RST_SHIFT_RSTn \
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} /* Reset bits for MRT peripheral */
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#define PINT_RSTS \
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{ \
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kPINT_RST_SHIFT_RSTn \
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} /* Reset bits for PINT peripheral */
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#define TRNG_RSTS \
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{ \
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kTRNG_RST_SHIFT_RSTn \
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} /* Reset bits for TRNG peripheral */
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#define SCT_RSTS \
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{ \
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kSCT_RST_SHIFT_RSTn \
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} /* Reset bits for SCT peripheral */
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#define UTICK_RSTS \
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{ \
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kUTICK_RST_SHIFT_RSTn \
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} /* Reset bits for UTICK peripheral */
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#define PLU_RSTS_N \
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{ \
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kPLU_RST_SHIFT_RSTn \
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} /* Reset bits for PLU peripheral */
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#define OSTIMER_RSTS \
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{ \
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kOSTIMER_RST_SHIFT_RSTn \
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} /* Reset bits for OSTIMER peripheral */
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#define POWERQUAD_RSTS \
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{ \
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kPOWERQUAD_RST_SHIFT_RSTn \
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} /* Reset bits for Powerquad peripheral */
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#define I3C_RSTS \
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{ \
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kI3C0_RST_SHIFT_RSTn, kI3C1_RST_SHIFT_RSTn \
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} /* Reset bits for I3C peripheral */
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typedef SYSCON_RSTn_t reset_ip_name_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @brief Assert reset to peripheral.
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*
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* Asserts reset signal to specified peripheral module.
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*
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* @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Clear reset to peripheral.
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*
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* Clears reset signal to specified peripheral module, allows it to operate.
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*
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* @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Reset peripheral module.
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*
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* Reset peripheral module.
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*
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* @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_PeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Release peripheral module.
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*
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* Release peripheral module.
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*
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* @param peripheral Peripheral to release. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
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{
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RESET_ClearPeripheralReset(peripheral);
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}
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#if defined(__cplusplus)
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}
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#endif
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/*! @} */
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#endif /* _FSL_RESET_H_ */
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