mirror of
https://github.com/cesanta/mongoose.git
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187 lines
6.5 KiB
C
187 lines
6.5 KiB
C
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// Copyright (c) 2022-2023 Cesanta Software Limited
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// All rights reserved
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//
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// MCU manual: RM0444, board manual: UM2591
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// https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
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// https://www.st.com/resource/en/user_manual/um2591-stm32g0-nucleo32-board-mb1455-stmicroelectronics.pdf
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// Alternate functions: https://www.st.com/resource/en/datasheet/stm32g031c6.pdf
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#pragma once
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// #define LED PIN('B', 3)
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#define LED PIN('C', 6)
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#ifndef UART_DEBUG
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#define UART_DEBUG USART2
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#endif
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#include <stm32g031xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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#define CPU_FREQUENCY 16000000
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#define AHB_FREQUENCY CPU_FREQUENCY
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#define APB_FREQUENCY CPU_FREQUENCY
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// #define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(PPRE1 - 3)))
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static inline void spin(volatile uint32_t n) {
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while (n--) (void) 0;
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}
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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#define GPIO(N) ((GPIO_TypeDef *) ((GPIOA_BASE) + 0x400 * (N)))
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static GPIO_TypeDef *gpio_bank(uint16_t pin) {
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return GPIO(PINBANK(pin));
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}
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static inline void gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int gpio_read(uint16_t pin) {
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return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->IOPENR |= BIT(PINBANK(pin)); // Enable GPIO clock
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SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline bool uart_init(USART_TypeDef *uart, unsigned long baud) {
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uint8_t af = 1; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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uint32_t freq = 0; // Bus frequency
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if (uart == USART1) {
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freq = CPU_FREQUENCY, RCC->APBENR2 |= RCC_APBENR2_USART1EN;
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tx = PIN('A', 9), rx = PIN('A', 10);
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} else if (uart == USART2) {
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freq = CPU_FREQUENCY, RCC->APBENR1 |= RCC_APBENR1_USART2EN;
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tx = PIN('A', 2), rx = PIN('A', 3);
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} else {
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return false;
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}
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gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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uart->CR1 = 0; // Disable UART
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uart->BRR = freq / baud; // Set baud rate
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uart->CR1 = USART_CR1_RE | USART_CR1_TE; // Set mode to TX & RX
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uart->CR1 |= USART_CR1_UE; // Enable UART
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return true;
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}
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static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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uart->TDR = byte;
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while ((uart->ISR & BIT(7)) == 0) spin(1);
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}
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static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(USART_TypeDef *uart) {
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return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->RDR & 255);
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}
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#ifndef RNG
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struct rng {
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volatile uint32_t CR, SR, DR;
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};
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#define RNG ((struct rng *) 0x40025000) // RM0444 2.2.2 Table 6
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#endif
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static inline void rng_init(void) {
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RCC->CCIPR |= 2U << 26U; // RNG clock source. Documented in 5.4.21
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RCC->AHBENR |= BIT(18); // RM0444 5.4.25 Table 36
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RNG->CR |= BIT(2); // 19.7.1
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}
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static inline uint32_t rng_read(void) {
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while ((RNG->SR & BIT(0)) == 0) (void) 0;
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return RNG->DR;
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}
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// Bit-bang SPI implementation
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struct spi {
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uint16_t miso, mosi, clk, cs; // Pins
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int spin; // Number of NOP spins for bitbanging
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};
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static inline void spi_begin(struct spi *spi) {
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gpio_write(spi->cs, 0);
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// printf("%s\n", __func__);
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}
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static inline void spi_end(struct spi *spi) {
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gpio_write(spi->cs, 1);
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// printf("%s\n", __func__);
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}
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static inline void spi_init(struct spi *spi) {
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gpio_input(spi->miso);
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gpio_output(spi->mosi);
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gpio_output(spi->clk);
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gpio_output(spi->cs);
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gpio_write(spi->cs, 1);
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// printf("%s\n", __func__);
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}
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// Send a byte, and return a received byte
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static inline uint8_t spi_txn(struct spi *spi, uint8_t write_byte) {
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unsigned count = spi->spin <= 0 ? 9 : (unsigned) spi->spin;
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uint8_t rx = 0, tx = write_byte;
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for (int i = 0; i < 8; i++) {
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gpio_write(spi->mosi, tx & 0x80U); // Set mosi
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gpio_write(spi->clk, 1); // Clock high
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spin(count); // Wait half cycle
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rx <<= 1U; // Shift alreay read bits
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if (gpio_read(spi->miso)) rx |= 1U; // Read next bit
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gpio_write(spi->clk, 0); // Clock low
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spin(count); // Wait half cycle
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tx <<= 1U; // Discard written bit
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}
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// printf("%s %02x %02x\n", __func__, (int) write_byte, (int) rx);
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return rx; // Return the received byte
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}
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#define UUID ((uint32_t *) UID_BASE) // Unique 96-bit chip ID. TRM 59.1
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// Helper macro for MAC generation, byte reads not allowed
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ \
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2, UUID[0] & 255, (UUID[0] >> 10) & 255, (UUID[0] >> 19) & 255, \
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UUID[1] & 255, UUID[2] & 255 \
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}
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