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H7 dual core OTA fix
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@ -6687,6 +6687,9 @@ static struct mg_flash s_mg_flash_stm32h7 = {
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#define FLASH_OPTSR_PRG 0x20
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#define FLASH_SIZE_REG 0x1ff1e880
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#define STM_DBGMCU_IDCODE 0x5C001000
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#define STM_DEV_ID (MG_REG(STM_DBGMCU_IDCODE) & (MG_BIT(12) - 1))
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MG_IRAM static bool is_dualbank(void) {
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return (s_mg_flash_stm32h7.size < 2 * 1024 * 1024) ? false : true;
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}
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@ -6773,6 +6776,12 @@ MG_IRAM static bool mg_stm32h7_swap(void) {
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flash_clear_err(bank);
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// printf("OPTSR_PRG 1 %#lx\n", FLASH->OPTSR_PRG);
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MG_SET_BITS(MG_REG(bank + FLASH_OPTSR_PRG), MG_BIT(31), desired);
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if (STM_DEV_ID == 0x450) {
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// H745/H755 and H747/H757 are running on dual core
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// Disable CM4 to prevent the old and the new firmwares from booting
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// simultaneously on each core.
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MG_SET_BITS(MG_REG(bank + FLASH_OPTSR_PRG), MG_BIT(22), 0);
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}
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// printf("OPTSR_PRG 2 %#lx\n", FLASH->OPTSR_PRG);
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MG_REG(bank + FLASH_OPTCR) |= MG_BIT(1); // OPTSTART
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while ((MG_REG(bank + FLASH_OPTSR_CUR) & MG_BIT(31)) != desired) (void) 0;
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@ -35,6 +35,9 @@ static struct mg_flash s_mg_flash_stm32h7 = {
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#define FLASH_OPTSR_PRG 0x20
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#define FLASH_SIZE_REG 0x1ff1e880
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#define STM_DBGMCU_IDCODE 0x5C001000
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#define STM_DEV_ID (MG_REG(STM_DBGMCU_IDCODE) & (MG_BIT(12) - 1))
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MG_IRAM static bool is_dualbank(void) {
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return (s_mg_flash_stm32h7.size < 2 * 1024 * 1024) ? false : true;
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}
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@ -121,6 +124,12 @@ MG_IRAM static bool mg_stm32h7_swap(void) {
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flash_clear_err(bank);
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// printf("OPTSR_PRG 1 %#lx\n", FLASH->OPTSR_PRG);
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MG_SET_BITS(MG_REG(bank + FLASH_OPTSR_PRG), MG_BIT(31), desired);
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if (STM_DEV_ID == 0x450) {
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// H745/H755 and H747/H757 are running on dual core
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// Disable CM4 to prevent the old and the new firmwares from booting
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// simultaneously on each core.
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MG_SET_BITS(MG_REG(bank + FLASH_OPTSR_PRG), MG_BIT(22), 0);
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}
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// printf("OPTSR_PRG 2 %#lx\n", FLASH->OPTSR_PRG);
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MG_REG(bank + FLASH_OPTCR) |= MG_BIT(1); // OPTSTART
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while ((MG_REG(bank + FLASH_OPTSR_CUR) & MG_BIT(31)) != desired) (void) 0;
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