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This commit is contained in:
Sergio R. Caprile
parent
4389ef1e77
commit
1479ebfb5d
@ -1,86 +1,29 @@
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CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
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CFLAGS += -Wformat-truncation -fno-common -Wconversion
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CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
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CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MIMXRT1176
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CFLAGS += -Icmsis_mcu/devices/MIMXRT1176/drivers -DCPU_MIMXRT1176DVMAA_cm7
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CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
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CFLAGS += -Wno-conversion -Wno-unused-parameter # due to NXP FSL code
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LDSCRIPT = link.ld
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LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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BOARD = rt1170
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IDE = GCC+make
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RTOS = baremetal
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WIZARD_URL ?= http://mongoose.ws/wizard
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SOURCES = main.c syscalls.c sysinit.c
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SOURCES += cmsis_mcu/devices/MIMXRT1176/gcc/startup_MIMXRT1176_cm7.S # NXP startup file. Compiler-dependent!
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SOURCES += cmsis_mcu/devices/MIMXRT1176/drivers/fsl_clock.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_anatop_ai.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_pmu.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_dcdc.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_common_arm.c # NXP support files
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CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS # Make startup code work as expected
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# Mongoose options are defined in mongoose_config.h
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SOURCES += mongoose.c net.c packed_fs.c
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# Example specific build options. See README.md
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CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\"
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ifeq ($(OS),Windows_NT)
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RM = cmd /C del /Q /F /S
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else
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RM = rm -rf
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endif
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all build example update: SOURCES += flash_image.c
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all build example: firmware.bin
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ram: LDSCRIPT = link_ram.ld
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ram: firmware.bin
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firmware.bin: wizard
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make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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wizard:
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hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
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&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
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unzip wizard.zip
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cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h
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firmware.elf: cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld link.ld Makefile
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
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arm-none-eabi-size $@
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flash: firmware.bin
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# flash
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cmsis_core: # ARM CMSIS core headers
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git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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cmsis_mcu:
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curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1176_DFP.18.0.0.pack -o $@.zip
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mkdir $@ && cd $@ && unzip -q ../$@.zip
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mbedtls: # mbedTLS library
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git clone --depth 1 -b v2.28.2 https://github.com/mbed-tls/mbedtls $@
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ifeq ($(TLS), mbedtls)
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CFLAGS += -DMG_TLS=MG_TLS_MBED -Wno-conversion -Imbedtls/include
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CFLAGS += -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" mbedtls/library/*.c
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firmware.elf: mbedtls
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endif
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# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
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DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/15
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update: firmware.bin
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
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update updateram: CFLAGS += -DUART_DEBUG=LPUART2
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test update: CFLAGS_EXTRA ="-DUART_DEBUG=LPUART2"
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test: update
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt
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grep 'READY, IP:' /tmp/output.txt # Check for network init
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updateram: ram
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @firmware.bin
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curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
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curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1"}'
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PC=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,4"}' | jq -r .resp[5:]` && \
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SP=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,0"}' | jq -r .resp[5:]` && \
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REQ="wm,e000ed08,0 wr,d,$$SP wr,f,$$PC" && \
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curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"'"$$REQ"'"}'
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curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0001"}'
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testram: updateram
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
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grep 'READY, IP:' /tmp/output.txt # Check for network init
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clean:
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$(RM) firmware.* *.su cmsis_core cmsis_mcu mbedtls *.zip
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rm -rf firmware.* wizard*
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1
examples/nxp/rt1170-evk-make-baremetal-builtin/README.md
Normal file
1
examples/nxp/rt1170-evk-make-baremetal-builtin/README.md
Normal file
@ -0,0 +1 @@
|
||||
See [Wizard](https://mongoose.ws/wizard/#/output?board=rt1020&ide=GCC+make&rtos=baremetal&file=README.md)
|
||||
@ -1,109 +0,0 @@
|
||||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define __DCD_DATA \
|
||||
0xD2, 0x04, 0xB8, 0x41, 0xCC, 0x04, 0x0C, 0x04, 0x40, 0xCC, 0x02, 0x00, \
|
||||
0x00, 0x00, 0x07, 0x03, 0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x18, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x24, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x30, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x3C, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x48, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x54, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x60, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x6C, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x78, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x84, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x90, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0x9C, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xA8, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10, \
|
||||
0x40, 0x0E, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xBC, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0xC4, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xC8, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xCC, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xD4, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xD8, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xE0, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xE4, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0xE8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xEC, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xF0, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x80, 0xF4, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xF8, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x0E, 0x80, 0xFC, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x58, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x64, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x70, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x7C, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x88, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x94, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xA0, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xAC, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xB8, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xC4, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xD0, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xDC, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xE8, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x82, 0xFC, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x00, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x83, 0x04, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x08, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x0C, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x83, 0x10, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x14, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x18, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x83, 0x1C, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x20, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x24, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x83, 0x28, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x2C, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x30, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x83, 0x34, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x38, \
|
||||
0x00, 0x00, 0x00, 0x08, 0x40, 0x0E, 0x83, 0x3C, 0x00, 0x00, 0x00, 0x08, \
|
||||
0x40, 0x0E, 0x83, 0x40, 0x00, 0x00, 0x00, 0x08, 0x40, 0x0D, 0x40, 0x00, \
|
||||
0x10, 0x00, 0x00, 0x04, 0x40, 0x0D, 0x40, 0x08, 0x00, 0x00, 0x00, 0x81, \
|
||||
0x40, 0x0D, 0x40, 0x0C, 0x00, 0x00, 0x00, 0x81, 0x40, 0x0D, 0x40, 0x10, \
|
||||
0x80, 0x00, 0x00, 0x1D, 0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x32, \
|
||||
0x40, 0x0D, 0x40, 0x44, 0x00, 0x77, 0x2A, 0x22, 0x40, 0x0D, 0x40, 0x48, \
|
||||
0x00, 0x01, 0x0A, 0x0D, 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x08, \
|
||||
0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x0D, 0x40, 0x94, \
|
||||
0x00, 0x00, 0x00, 0x02, 0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, 0xC0, 0x00, 0x04, 0x00, \
|
||||
0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, \
|
||||
0xC0, 0x00, 0x04, 0x00, 0xCC, 0x00, 0x14, 0x04, 0x40, 0x0D, 0x40, 0x3C, \
|
||||
0x00, 0x00, 0x00, 0x03, 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, \
|
||||
0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, \
|
||||
0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, 0xCC, 0x00, 0x14, 0x04, \
|
||||
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, 0x40, 0x0D, 0x40, 0x9C, \
|
||||
0xA5, 0x5A, 0x00, 0x0C, 0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, \
|
||||
0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, \
|
||||
0xCC, 0x00, 0x1C, 0x04, 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, \
|
||||
0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33, 0x40, 0x0D, 0x40, 0x9C, \
|
||||
0xA5, 0x5A, 0x00, 0x0A, 0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, \
|
||||
0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, 0xC0, 0x00, 0x04, 0x00, \
|
||||
0xCC, 0x00, 0x14, 0x04, 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, \
|
||||
0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09
|
||||
@ -1,61 +0,0 @@
|
||||
#include "dcd.h" // pin settings for MIMXRT1060-EVKB board
|
||||
#include "fsl_flexspi.h" // peripheral structures
|
||||
#include "fsl_romapi.h" // peripheral structures
|
||||
#include "hal.h"
|
||||
|
||||
extern uint32_t __isr_vector[];
|
||||
|
||||
// RM 10.7.2
|
||||
__attribute__((section(".dcd"), used))
|
||||
const uint8_t __ivt_dcd_data[] = {__DCD_DATA};
|
||||
|
||||
// RM 10.7.1
|
||||
__attribute__((section(".dat"), used)) const uint32_t __ivt_boot_data[] = {
|
||||
FlexSPI1_AMBA_BASE, // boot start location
|
||||
64 * 1024 * 1024, // size
|
||||
0, // Plugin flag
|
||||
0Xffffffff // empty - extra data word
|
||||
};
|
||||
|
||||
__attribute__((section(".ivt"), used)) const uint32_t __ivt[8] = {
|
||||
0x412000d1, // header: 41 - version, 2000 size, d1 tag
|
||||
(uint32_t) __isr_vector, // entry
|
||||
0, // reserved
|
||||
(uint32_t) __ivt_dcd_data, // dcd
|
||||
(uint32_t) __ivt_boot_data, // boot data
|
||||
(uint32_t) __ivt, // this is us - ivt absolute address
|
||||
0, // csf absolute address
|
||||
0, // reserved for HAB
|
||||
};
|
||||
|
||||
#define __FLEXSPI_QSPI_LUT { \
|
||||
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20),\
|
||||
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),\
|
||||
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),\
|
||||
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),\
|
||||
[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x21, RADDR_SDR, FLEXSPI_1PAD, 0x20),\
|
||||
[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),\
|
||||
[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x12, RADDR_SDR, FLEXSPI_1PAD, 0x20),\
|
||||
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),\
|
||||
[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),\
|
||||
}
|
||||
|
||||
// MIMXRT1170-EVKB flash chip config: W25Q512NWEIQ
|
||||
__attribute__((section(".cfg"), used))
|
||||
const flexspi_nor_config_t __qspi_flash_cfg = {
|
||||
.memConfig = {.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = 1, // ReadSampleClk_LoopbackFromDqsPad
|
||||
.csHoldTime = 3,
|
||||
.csSetupTime = 3,
|
||||
.controllerMiscOption = BIT(4),
|
||||
.deviceType = 1, // serial NOR
|
||||
.sflashPadType = 4,
|
||||
.serialClkFreq = 7, // 133MHz
|
||||
.sflashA1Size = 64 * 1024 * 1024,
|
||||
.lookupTable = __FLEXSPI_QSPI_LUT},
|
||||
.pageSize = 256,
|
||||
.sectorSize = 4 * 1024,
|
||||
.ipcmdSerialClkFreq = 1,
|
||||
.blockSize = 64 * 1024,
|
||||
.isUniformBlockSize = false};
|
||||
@ -1,337 +0,0 @@
|
||||
// Copyright (c) 2024 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
// https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM
|
||||
// https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKBHUG
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "MIMXRT1176_cm7.h"
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
|
||||
#define PIN(bank, num) ((((bank) - '0') << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
// Use LED for blinking, D6: GPIO_AD_04. GPIO3.3 (schematics, RM)
|
||||
#define LED PIN('3', 3)
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG LPUART1
|
||||
#endif
|
||||
|
||||
// No settable constants, see sysinit.c
|
||||
#define SYS_FREQUENCY 996000000UL
|
||||
|
||||
static inline void spin(volatile uint32_t count) {
|
||||
while (count--) (void) 0;
|
||||
}
|
||||
|
||||
// Use "Unassigned/Domain Mode"
|
||||
static inline void clock_periph(uint32_t index, bool val) {
|
||||
CCM->LPCG[index].DIRECT = val ? 1 : 0; // (15.9.1.25)
|
||||
}
|
||||
|
||||
// which peripheral feeds the pin
|
||||
static inline void gpio_mux_config(uint16_t index, uint8_t af) {
|
||||
IOMUXC->SW_MUX_CTL_PAD[index] = af;
|
||||
}
|
||||
|
||||
// which pin feeds the peripheral (2nd stage)
|
||||
static inline void periph_mux_config(uint16_t index, uint8_t in) {
|
||||
IOMUXC->SELECT_INPUT[index] = in;
|
||||
}
|
||||
|
||||
// CM7_GPIOx not supported
|
||||
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
|
||||
enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH };
|
||||
enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
|
||||
static inline GPIO_Type *gpio_bank(uint16_t pin) {
|
||||
static const GPIO_Type *g[] = {NULL, GPIO1, GPIO2, GPIO3, GPIO4,
|
||||
GPIO5, GPIO6, GPIO7, GPIO8, GPIO9,
|
||||
GPIO10, GPIO11, GPIO12, GPIO13};
|
||||
return (GPIO_Type *) g[PINBANK(pin)];
|
||||
}
|
||||
|
||||
// pin driver/pull-up/down configuration (allow both cores)
|
||||
static inline void gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed,
|
||||
uint8_t pull) {
|
||||
if (index < kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 ||
|
||||
(index >= kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 &&
|
||||
index < kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00)) {
|
||||
IOMUXC->SW_PAD_CTL_PAD[index] =
|
||||
IOMUXC_SW_PAD_CTL_PAD_PDRV(speed == GPIO_SPEED_LOW) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_ODE(type) | IOMUXC_SW_PAD_CTL_PAD_PULL(pull);
|
||||
} else {
|
||||
bool dopull = pull > 0;
|
||||
if (dopull) pull = (pull == GPIO_PULL_UP);
|
||||
IOMUXC->SW_PAD_CTL_PAD[index] =
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(speed != GPIO_SPEED_LOW) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_ODE(type) | IOMUXC_SW_PAD_CTL_PAD_PUE(dopull) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PUS(pull) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint8_t bit = (uint8_t) PINNO(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
|
||||
clock_periph(51, 1); // clk_enable_gpio (15.5.4 Table 15-5)
|
||||
clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
|
||||
switch (PINBANK(pin)) { // (11.1.1 Table 11-1)
|
||||
case 1:
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 + bit, type, speed,
|
||||
pull);
|
||||
break;
|
||||
case 2:
|
||||
IOMUXC_GPR->GPR40 = 0; // select GPIO2
|
||||
IOMUXC_GPR->GPR41 = 0; // select GPIO2
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 + bit, type, speed,
|
||||
pull);
|
||||
break;
|
||||
case 3:
|
||||
IOMUXC_GPR->GPR42 = 0; // select GPIO3
|
||||
IOMUXC_GPR->GPR43 = 0; // select GPIO3
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 + bit, type, speed,
|
||||
pull);
|
||||
break;
|
||||
case 4:
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 + bit, type, speed,
|
||||
pull);
|
||||
break;
|
||||
default:
|
||||
// TODO(): support GPIO5-13, 10-15 requires redefinition of PIN() macro
|
||||
break;
|
||||
}
|
||||
|
||||
gpio->IMR &= ~mask;
|
||||
if (mode == GPIO_MODE_INPUT) {
|
||||
gpio->GDIR &= ~mask;
|
||||
} else {
|
||||
gpio->GDIR |= mask;
|
||||
}
|
||||
}
|
||||
static inline void gpio_input(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_NONE);
|
||||
}
|
||||
static inline void gpio_output(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
static inline bool gpio_read(uint16_t pin) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
return gpio->DR & mask;
|
||||
}
|
||||
static inline void gpio_write(uint16_t pin, bool value) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
if (value) {
|
||||
gpio->DR |= mask;
|
||||
} else {
|
||||
gpio->DR &= ~mask;
|
||||
}
|
||||
}
|
||||
static inline void gpio_toggle(uint16_t pin) {
|
||||
gpio_write(pin, !gpio_read(pin));
|
||||
}
|
||||
|
||||
// 15.3 Table 15-2: uart_clk_root
|
||||
// 15.4: lpuart*_clk_root 15.5.3 Table 15-4; 15.9.1.2; select OSC_24M
|
||||
static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
|
||||
uint8_t af = 0; // Alternate function
|
||||
uint16_t mr = 0, pr = 0, mt = 0, pt = 0; // pins
|
||||
uint32_t freq = 24000000; // uart_clk_root frequency
|
||||
if (uart == LPUART1) {
|
||||
af = 0;
|
||||
mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24;
|
||||
pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24;
|
||||
mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25;
|
||||
pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25;
|
||||
// configure clock root source and divisor /1, enable peripheral clock
|
||||
CCM->CLOCK_ROOT[25].CONTROL =
|
||||
CCM_CLOCK_ROOT_CONTROL_MUX(1) | CCM_CLOCK_ROOT_CONTROL_DIV(0);
|
||||
clock_periph(86, 1); // (15.5.4 Table 15-5)
|
||||
periph_mux_config(kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT, 0);
|
||||
periph_mux_config(kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT, 0);
|
||||
} else if (uart == LPUART2) {
|
||||
af = 2;
|
||||
mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10;
|
||||
pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10;
|
||||
mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11;
|
||||
pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11;
|
||||
CCM->CLOCK_ROOT[26].CONTROL =
|
||||
CCM_CLOCK_ROOT_CONTROL_MUX(1) | CCM_CLOCK_ROOT_CONTROL_DIV(0);
|
||||
clock_periph(87, 1); // (15.5.4 Table 15-5)
|
||||
}
|
||||
clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
|
||||
gpio_mux_config(mt, af);
|
||||
gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_NONE);
|
||||
gpio_mux_config(mr, af);
|
||||
gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
|
||||
uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
|
||||
uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
|
||||
uart->BAUD = LPUART_BAUD_OSR(16 - 1) |
|
||||
LPUART_BAUD_SBR(freq / (16 * baud)); // Rx sample at 16x
|
||||
uart->CTRL = LPUART_CTRL_IDLECFG(1) |
|
||||
LPUART_CTRL_ILT(1); // no parity, idle 2 chars after 1 stop bit
|
||||
uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
|
||||
}
|
||||
|
||||
static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
|
||||
uart->DATA = byte;
|
||||
while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
|
||||
}
|
||||
static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int uart_read_ready(LPUART_Type *uart) {
|
||||
(void) uart;
|
||||
return uart->STAT & LPUART_STAT_RDRF_MASK;
|
||||
}
|
||||
static inline uint8_t uart_read_byte(LPUART_Type *uart) {
|
||||
return (uint8_t) (uart->DATA & 255);
|
||||
}
|
||||
|
||||
|
||||
static inline void lpsr_mux_config(uint16_t index, uint8_t af) {
|
||||
IOMUXC_LPSR->SW_MUX_CTL_PAD[index] = af;
|
||||
}
|
||||
|
||||
static inline void lpsr_pad_config(uint16_t index, uint8_t type, uint8_t speed,
|
||||
uint8_t pull) {
|
||||
bool dopull = pull > 0;
|
||||
if (dopull) pull = (pull == GPIO_PULL_UP);
|
||||
IOMUXC_LPSR->SW_PAD_CTL_PAD[index] =
|
||||
IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(speed != GPIO_SPEED_LOW) |
|
||||
IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(type) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PUE(dopull) | IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(pull) |
|
||||
IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH);
|
||||
}
|
||||
|
||||
#include "fsl_clock.h"
|
||||
|
||||
// - 15.4 clock tree
|
||||
// - 15.3 Table 15-2: ENET1_CLK_ROOT <= 50MHz
|
||||
// - PHY has no xtal, XI driven from ENET_REF_CLK (labeled as ENET_TX_REF_CLK
|
||||
// (GPIO_DISP_B2_05)), generated by the MCU
|
||||
// - PHY RST connected to GPIO12.12 (GPIO_LPSR_12);
|
||||
// - 60.4 REF_CLK is RMII mode reference clock for Rx, Tx, and SMI; it is I/O
|
||||
static inline void ethernet_init(void) {
|
||||
const clock_sys_pll1_config_t pll1 = {.pllDiv2En = true};
|
||||
CLOCK_InitSysPll1(&pll1); // setup PLL1 and clock ENET from it
|
||||
// configure clock root source PLL1/2 and divisor /10, enable peripheral clock
|
||||
CCM->CLOCK_ROOT[51].CONTROL =
|
||||
CCM_CLOCK_ROOT_CONTROL_MUX(4) | CCM_CLOCK_ROOT_CONTROL_DIV(10 - 1);
|
||||
clock_periph(112, 1); // clk_enable_enet (15.5.4 Table 15-5)
|
||||
|
||||
clock_periph(51, 1); // clk_enable_gpio (15.5.4 Table 15-5)
|
||||
clock_periph(50, 1); // clk_enable_iomuxc_lpsr (15.5.4 Table 15-5)
|
||||
clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
|
||||
lpsr_mux_config(kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12,
|
||||
10); // set GPIO12.12 as GPIO (PHY \RST)
|
||||
lpsr_pad_config(kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12,
|
||||
GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
GPIO12->IMR &= ~BIT(12);
|
||||
GPIO12->GDIR |= BIT(12);
|
||||
GPIO12->DR &= ~BIT(12); // reset PHY
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05,
|
||||
2); // set for ENET_REF_CLK
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05] |=
|
||||
IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT,
|
||||
1); // drive peripheral from DISP_B2_05, so RMII clock is
|
||||
// taken from ENET_REF_CLK
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
IOMUXC_GPR->GPR4 |=
|
||||
IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(1); // Set ENET_REF_CLK as output
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06,
|
||||
1); // set for RXDATA0
|
||||
periph_mux_config(kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0,
|
||||
1); // drive peripheral from DISP_B2_06
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07,
|
||||
1); // set for RXDATA1
|
||||
periph_mux_config(kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1,
|
||||
1); // drive peripheral from DISP_B2_07
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08, 1); // set for CRS
|
||||
periph_mux_config(kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT,
|
||||
1); // drive peripheral from DISP_B2_08
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09, 1); // set for RXERR
|
||||
periph_mux_config(kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT,
|
||||
1); // drive peripheral from DISP_B2_09
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02,
|
||||
1); // set for TXDATA0
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03,
|
||||
1); // set for TXDATA1
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04, 1); // set for TXEN
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32, 3); // set for MDC
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33, 3); // set for MDIO
|
||||
periph_mux_config(kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT,
|
||||
1); // drive peripheral from AD_33
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
|
||||
IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_ENET_MASK; // ERR050396
|
||||
gpio_init(PIN('3', 11), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_UP); // setup IRQ (pulled-up)(not used)
|
||||
spin(10000); // keep PHY RST low for a while
|
||||
GPIO12->DR |= BIT(12); // deassert RST
|
||||
|
||||
clock_periph(112, 1); // clk_enable_enet (15.5.4 Table 15-5)
|
||||
NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler
|
||||
}
|
||||
|
||||
// Helper macro for MAC generation, byte reads not allowed
|
||||
#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
|
||||
{ \
|
||||
2, OCOTP->FUSEN[16].FUSE & 255, (OCOTP->FUSEN[16].FUSE >> 10) & 255, \
|
||||
((OCOTP->FUSEN[16].FUSE >> 19) ^ (OCOTP->FUSEN[17].FUSE >> 19)) & 255, \
|
||||
(OCOTP->FUSEN[17].FUSE >> 10) & 255, OCOTP->FUSEN[17].FUSE & 255 \
|
||||
}
|
||||
|
||||
static inline void flash_init(void) { // QSPI in FlexSPI
|
||||
// set pins
|
||||
clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
|
||||
#if 0
|
||||
#endif
|
||||
}
|
||||
@ -1,24 +0,0 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash_hdr(rx) : ORIGIN = 0x30000000, LENGTH = 8k
|
||||
flash_irq(rx) : ORIGIN = 0x30002000, LENGTH = 1k
|
||||
flash_code(rx) : ORIGIN = 0x30002400, LENGTH = 65527k
|
||||
|
||||
itcram(rx) : ORIGIN = 0x00000000, LENGTH = 256k
|
||||
dtcram(rw) : ORIGIN = 0x20000000, LENGTH = 256k
|
||||
ocram(rw) : ORIGIN = 0x20240000, LENGTH = 512k /* Is this cached ? */
|
||||
}
|
||||
__StackTop = ORIGIN(dtcram) + LENGTH(dtcram);
|
||||
|
||||
/* TODO(): separate itcram and go back to using dtcram for data and bss when ota is finished */
|
||||
|
||||
SECTIONS {
|
||||
.hdr : { FILL(0xff) ; . = 0x400 ; KEEP(*(.cfg)) . = 0x1000 ; KEEP(*(.ivt)) . = 0x1020 ;
|
||||
KEEP(*(.dat)) . = 0x1030 ; KEEP(*(.dcd)) . = 0x2000 ;} >flash_hdr
|
||||
.irq : { KEEP(*(.isr_vector)) } > flash_irq
|
||||
.text : { *(.text* .text.*) *(.rodata*) ; } > flash_code
|
||||
.data : { __data_start__ = .; *(.data SORT(.data.*)) *(.iram) __data_end__ = .; } > itcram AT > flash_code
|
||||
__etext = LOADADDR(.data);
|
||||
.bss : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > itcram
|
||||
_end = .;
|
||||
}
|
||||
@ -1,61 +0,0 @@
|
||||
// Copyright (c) 2024 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
#include "net.h"
|
||||
|
||||
#define BLINK_PERIOD_MS 1000 // LED blinking period in millis
|
||||
|
||||
static volatile uint64_t s_ticks; // Milliseconds since boot
|
||||
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
|
||||
s_ticks++;
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) { // Let Mongoose use our uptime function
|
||||
return s_ticks; // Return number of milliseconds since boot
|
||||
}
|
||||
|
||||
static void timer_fn(void *arg) {
|
||||
gpio_toggle(LED); // Blink LED
|
||||
(void) arg;
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
gpio_output(LED); // Setup blue LED
|
||||
uart_init(UART_DEBUG, 115200); // Initialise debug printf
|
||||
ethernet_init(); // Initialise ethernet pins
|
||||
MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000));
|
||||
|
||||
struct mg_mgr mgr; // Initialise
|
||||
mg_mgr_init(&mgr); // Mongoose event manager
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level
|
||||
|
||||
// Initialise Mongoose network stack
|
||||
struct mg_tcpip_driver_imxrt_data driver_data = {.mdc_cr = 24, .phy_addr = 3};
|
||||
struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
|
||||
// Uncomment below for static configuration:
|
||||
// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
|
||||
// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
|
||||
// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
|
||||
.driver = &mg_tcpip_driver_imxrt,
|
||||
.driver_data = &driver_data};
|
||||
mg_tcpip_init(&mgr, &mif);
|
||||
mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, NULL);
|
||||
|
||||
MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
|
||||
while (mif.state != MG_TCPIP_STATE_READY) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
MG_INFO(("Initialising application..."));
|
||||
web_init(&mgr);
|
||||
|
||||
|
||||
MG_INFO(("Starting event loop"));
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.c
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.h
|
||||
@ -1,15 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_NEWLIB
|
||||
#define MG_OTA MG_OTA_RT1060
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_DRIVER_IMXRT 1
|
||||
#define MG_DRIVER_IMXRT_RT11 1
|
||||
#define MG_ENABLE_TCPIP_DRIVER_INIT 0
|
||||
#define MG_IO_SIZE 256
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 0
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
#define MG_ENABLE_TCPIP_PRINT_DEBUG_STATS 1
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.c
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.h
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/packed_fs.c
|
||||
@ -1,98 +0,0 @@
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
int _fstat(int fd, struct stat *st) {
|
||||
if (fd < 0) return -1;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
extern char _end;
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
unsigned char x = 0, *heap_end = (unsigned char *)((size_t) &x - 512);
|
||||
(void) x;
|
||||
if (heap == NULL) heap = (unsigned char *) &_end;
|
||||
prev_heap = heap;
|
||||
if (heap + incr > heap_end) return (void *) -1;
|
||||
heap += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int mkdir(const char *path, mode_t mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {}
|
||||
|
||||
extern uint64_t mg_now(void);
|
||||
|
||||
int _gettimeofday(struct timeval *tv, void *tz) {
|
||||
uint64_t now = mg_now();
|
||||
(void) tz;
|
||||
tv->tv_sec = (time_t) (now / 1000);
|
||||
tv->tv_usec = (unsigned long) ((now % 1000) * 1000);
|
||||
return 0;
|
||||
}
|
||||
@ -1,48 +0,0 @@
|
||||
// Copyright (c) 2024 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// This file contains essentials required by the CMSIS:
|
||||
// uint32_t SystemCoreClock - holds the system core clock value
|
||||
// SystemInit() - initialises the system, e.g. sets up clocks
|
||||
|
||||
#include "hal.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "fsl_dcdc.h"
|
||||
#include "fsl_pmu.h"
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
|
||||
// - 15.4 clock tree
|
||||
// 15.4: M7_CLK_ROOT
|
||||
// 15.5.3 Table 15-4; 15.9.1.2; select PLL_ARM_CLK
|
||||
// 15.8.2 PLL Enable Sequence
|
||||
// - Datasheet 4.1.3, Table 11: "Overdrive" run mode particulars
|
||||
void SystemInit(void) { // Called automatically by startup code (ints masked)
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
asm("DSB");
|
||||
asm("ISB");
|
||||
// 79.5.2: Disable watchdogS after reset (unlocked)
|
||||
RTWDOG3->CS &= ~RTWDOG_CS_EN_MASK;
|
||||
RTWDOG3->TOVAL = 0xFFFF;
|
||||
while (RTWDOG3->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock
|
||||
while ((RTWDOG3->CS & RTWDOG_CS_RCS_MASK) == 0)
|
||||
spin(1); // wait for new config
|
||||
RTWDOG4->CS &= ~RTWDOG_CS_EN_MASK;
|
||||
RTWDOG4->TOVAL = 0xFFFF;
|
||||
while (RTWDOG4->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock
|
||||
while ((RTWDOG4->CS & RTWDOG_CS_RCS_MASK) == 0)
|
||||
spin(1); // wait for new config
|
||||
ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1);
|
||||
while ((ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK) == 0)
|
||||
spin(1); // wait until it is stable
|
||||
DCDC_BootIntoDCM(DCDC); // Enable "overdrive" mode as needed
|
||||
DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
|
||||
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, (OCOTP->FUSEN[7].FUSE & BIT(4)) == 0);
|
||||
const clock_arm_pll_config_t armpll = {.loopDivider = 166, .postDivider = 0};
|
||||
CLOCK_InitArmPll(&armpll); // Set clock to 996MHz
|
||||
CCM->CLOCK_ROOT[0].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(4); // /1
|
||||
|
||||
// rng_init(); // TRNG is part or CAAM and there is no info on that
|
||||
// NXP startup code calls SystemInit BEFORE initializing RAM...
|
||||
SysTick_Config(SYS_FREQUENCY / 1000); // Sys tick every 1ms
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user