Use CMSIS headers for f429 and f746 baremetal examples

examples/device-dashboard/Makefile

@@ -1,40 +1,33 @@
-PROG ?= example
+SOURCES = ../../mongoose.c main.c net.c packed_fs.c
-SOURCES ?= ../../mongoose.c main.c net.c packed_fs.c
+CFLAGS = -W -Wall -Wextra -g
-CFLAGS ?= -I../.. -DMG_ENABLE_PACKED_FS=1 -DMG_ENABLE_LINES=1 $(EXTRA)
-FILES_TO_EMBED ?= $(wildcard web_root/*)
-ROOT ?= $(realpath $(CURDIR)/../../..)
-DOCKER ?= docker run --rm -e Tmp=. -e WINEDEBUG=-all -v $(ROOT):$(ROOT) -w $(CURDIR)
-VC98 ?= $(DOCKER) mdashnet/vc98 wine
-MINGW ?= $(DOCKER) mdashnet/mingw
 
-ifeq "$(SSL)" "MBEDTLS"
+# Mongoose build options. See https://mongoose.ws/documentation/#build-options
-CFLAGS  += -DMG_ENABLE_MBEDTLS=1 -I$(MBEDTLS)/include -L$(MBEDTLS)/lib -lmbedtls -lmbedcrypto -lmbedx509
+CFLAGS += -I ../.. -DMG_ENABLE_PACKED_FS=1
-endif
 
-ifeq "$(SSL)" "OPENSSL"
+ifeq ($(OS),Windows_NT)
-CFLAGS  += -DMG_ENABLE_OPENSSL=1 -I$(OPENSSL)/include -L$(OPENSSL)/lib -lssl -lcrypto
+  # Windows settings. Assume MinGW compiler
+  PROG ?= example.exe           # Use .exe suffix for the binary
+  CC = gcc                      # Use MinGW gcc compiler
+  CFLAGS += -lws2_32            # Link against Winsock library
+  DELETE = cmd /C del /Q /F /S  # Command prompt command to delete files
+else
+  # Mac, Linux
+  PROG ?= example
+  DELETE = rm -rf
 endif
 
 all: $(PROG)
-	$(RUN) ./$(PROG)
+	$(RUN) ./$(PROG) $(ARGS)
 
-$(PROG): $(SOURCES) $(FILES_TO_EMBED)
+# Before embedding files, gzip them to save space
+packed_fs.c: $(shell find web_root -type f) Makefile
+	rm -rf tmp/web_root && mkdir tmp && cp -r web_root tmp/
+	find tmp -type f | xargs -n1 gzip
 	$(CC) ../../test/pack.c -o pack
-	./pack $(FILES_TO_EMBED) > packed_fs.c
+	cd tmp && ../pack `find web_root -type f` > ../$@
-	$(CC) -W -Wall -Wextra -O0 -g3 $(CFLAGS) -o $(PROG) $(SOURCES)
 
-
+$(PROG): $(SOURCES)
-mingw: $(SOURCES) $(FILES_TO_EMBED)
+	$(CC) $(SOURCES) $(CFLAGS) $(CFLAGS_EXTRA) -o $@
-	$(MINGW) i686-w64-mingw32-gcc $(CFLAGS) ../../test/pack.c -o pack.exe
-	$(MINGW) wine cmd /c 'pack.exe $(FILES_TO_EMBED) > packed_fs.c'
-	$(MINGW) i686-w64-mingw32-gcc $(CFLAGS) $(SOURCES) -lws2_32 -o $(PROG).exe
-	$(MINGW) wine $(PROG).exe
-
-vc98: $(SOURCES) $(FILES_TO_EMBED)
-	$(VC98) cl.exe /nologo $(CFLAGS) ../../test/pack.c /Fepack.exe
-	$(VC98) cmd /c 'pack.exe $(FILES_TO_EMBED) > packed_fs.c'
-	$(VC98) cl.exe /nologo /O2 $(CFLAGS) $(SOURCES) /Fe$(PROG).exe
-	$(VC98) $(PROG).exe
 
 clean:
-	rm -rf $(PROG) *.o *.dSYM *.gcov *.gcno *.gcda *.obj *.exe *.ilk *.pdb log.txt pack
+	$(DELETE) $(PROG) *.dSYM pack tmp

examples/stm32/nucleo-f429zi-baremetal/Makefile

@@ -1,44 +1,60 @@
-CFLAGS  ?=  -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \
+# Download CMSIS header files from Github on demand
-						-Wformat-truncation -fno-common -Wconversion \
+CMSIS_CORE_VERSION ?= 5.9.0      # ARM Cortex-M definitions
-						-g3 -Os -ffunction-sections -fdata-sections -I. \
+CMSIS_CORE_REPO ?= https://github.com/ARM-software/CMSIS_5
-						-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 $(EXTRA_CFLAGS)
+CMSIS_DEVICE_VERSION ?= v2.6.8   # ST MCU peripheral definitions
-LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
+CMSIS_DEVICE_REPO ?= https://github.com/STMicroelectronics/cmsis_device_f4
-SOURCES = boot.c main.c syscalls.c
 
-# Add Mongoose-specific flags and source files
+CFLAGS ?= -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \
+          -Wformat-truncation -fno-common -Wconversion \
+          -g3 -Os -ffunction-sections -fdata-sections \
+          -I . -I cmsis_core/CMSIS/Core/Include -I cmsis_device_f4/Include \
+          -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 $(EXTRA_CFLAGS)
+LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
+SOURCES = main.c syscalls.c cmsis_device_f4/Source/Templates/gcc/startup_stm32f429xx.s
+
+# Mongoose-specific build flags and source code files
+# Build options reference: https://mongoose.ws/documentation/#build-options
 CFLAGS  += -I../../.. -DMG_ARCH=MG_ARCH_NEWLIB -DMG_ENABLE_CUSTOM_MILLIS=1 -DMG_ENABLE_MIP=1 -DMG_ENABLE_PACKED_FS=1
 SOURCES += ../../../mongoose.c ../../device-dashboard/net.c ../../device-dashboard/packed_fs.c
 
+# Build flashable .bin file
 all build example: firmware.bin
 
+# .bin file is made from .elf file, by concatenating .text and .data sections
 firmware.bin: firmware.elf
 	arm-none-eabi-objcopy -O binary $< $@
 
-firmware.elf: $(SOURCES) mcu.h
+# .elf file is produced by compiling sources
+firmware.elf: $(SOURCES) hal.h link.ld cmsis_core cmsis_device_f4
 	arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
 
-# Note: on "unknown chip id" flash error, wire BOOT0 to VDD and st-flash erase
+# Flash .bin file to the target board via the built-in debugger
 flash: firmware.bin
 	st-flash --reset write $< 0x8000000
 
+# Download ST's CMSIS headers with peripheral definitions
+cmsis_device_f4/Source/Templates/gcc/startup_stm32f429xx.s: cmsis_device_f4
+cmsis_device_f4:
+	git clone --depth 1 -b $(CMSIS_DEVICE_VERSION) $(CMSIS_DEVICE_REPO) $@
+
+# Download ARM's CMSIS headers with core Cortex-M definitions
+cmsis_core:
+	git clone --depth 1 -b $(CMSIS_CORE_VERSION) $(CMSIS_CORE_REPO) $@
+
 # Requires env variable VCON_API_KEY set
 DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/2
 
 # Upload firmware to a remote test device
 update: firmware.bin
-	curl --fail -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
 
 # Read serial port on a remote test device for 5 seconds, store in a
 # temporary file, and check the output for expected patterns
 test:	EXTRA_CFLAGS += -DUART_DEBUG=UART1
 test: update
-	curl --fail -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
 	grep 'Ethernet: up' /tmp/output.txt     # Check for network init
 	grep 'MQTT connected' /tmp/output.txt   # Check for MQTT connection success
 
-# Read serial port on a remote test device for 5 seconds
-tx:
-	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5
-
 clean:
-	@rm -rf firmware.* *.su
+	@rm -rf firmware.* *.su cmsis_core cmsis_device_f4

examples/stm32/nucleo-f429zi-baremetal/boot.c

@@ -1,160 +0,0 @@
-// Copyright (c) 2022 Cesanta Software Limited
-// All rights reserved
-
-// Startup code
-__attribute__((naked, noreturn)) void _reset(void) {
-  // Initialise memory
-  extern long _sbss, _ebss, _sdata, _edata, _sidata;
-  for (long *src = &_sbss; src < &_ebss; src++) *src = 0;
-  for (long *src = &_sdata, *dst = &_sidata; src < &_edata;) *src++ = *dst++;
-
-  // Call main()
-  extern void main(void);
-  main();
-  for (;;) (void) 0;
-}
-
-void __attribute__((weak)) DefaultIRQHandler(void) {
-  for (;;) (void) 0;
-}
-
-#define WEAK_ALIAS __attribute__((weak, alias("DefaultIRQHandler")))
-
-WEAK_ALIAS void NMI_Handler(void);
-WEAK_ALIAS void HardFault_Handler(void);
-WEAK_ALIAS void MemManage_Handler(void);
-WEAK_ALIAS void BusFault_Handler(void);
-WEAK_ALIAS void UsageFault_Handler(void);
-WEAK_ALIAS void SVC_Handler(void);
-WEAK_ALIAS void DebugMon_Handler(void);
-WEAK_ALIAS void PendSV_Handler(void);
-WEAK_ALIAS void SysTick_Handler(void);
-
-WEAK_ALIAS void WWDG_IRQHandler(void);
-WEAK_ALIAS void PVD_IRQHandler(void);
-WEAK_ALIAS void TAMP_STAMP_IRQHandler(void);
-WEAK_ALIAS void RTC_WKUP_IRQHandler(void);
-WEAK_ALIAS void FLASH_IRQHandler(void);
-WEAK_ALIAS void RCC_IRQHandler(void);
-WEAK_ALIAS void EXTI0_IRQHandler(void);
-WEAK_ALIAS void EXTI1_IRQHandler(void);
-WEAK_ALIAS void EXTI2_IRQHandler(void);
-WEAK_ALIAS void EXTI3_IRQHandler(void);
-WEAK_ALIAS void EXTI4_IRQHandler(void);
-WEAK_ALIAS void EXTI9_5_IRQHandler(void);
-WEAK_ALIAS void EXTI15_10_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream0_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream1_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream2_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream3_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream4_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream5_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream6_IRQHandler(void);
-WEAK_ALIAS void ADC_IRQHandler(void);
-WEAK_ALIAS void CAN1_TX_IRQHandler(void);
-WEAK_ALIAS void CAN1_RX0_IRQHandler(void);
-WEAK_ALIAS void CAN1_RX1_IRQHandler(void);
-WEAK_ALIAS void CAN1_SCE_IRQHandler(void);
-WEAK_ALIAS void TIM1_BRK_TIM9_IRQHandler(void);
-WEAK_ALIAS void TIM1_UP_TIM10_IRQHandler(void);
-WEAK_ALIAS void TIM1_TRG_COM_TIM11_IRQHandler(void);
-WEAK_ALIAS void TIM1_CC_IRQHandler(void);
-WEAK_ALIAS void TIM2_IRQHandler(void);
-WEAK_ALIAS void TIM3_IRQHandler(void);
-WEAK_ALIAS void TIM4_IRQHandler(void);
-WEAK_ALIAS void I2C1_EV_IRQHandler(void);
-WEAK_ALIAS void I2C1_ER_IRQHandler(void);
-WEAK_ALIAS void I2C2_EV_IRQHandler(void);
-WEAK_ALIAS void I2C2_ER_IRQHandler(void);
-WEAK_ALIAS void SPI1_IRQHandler(void);
-WEAK_ALIAS void SPI2_IRQHandler(void);
-WEAK_ALIAS void USART1_IRQHandler(void);
-WEAK_ALIAS void USART2_IRQHandler(void);
-WEAK_ALIAS void USART3_IRQHandler(void);
-WEAK_ALIAS void RTC_Alarm_IRQHandler(void);
-WEAK_ALIAS void OTG_FS_WKUP_IRQHandler(void);
-WEAK_ALIAS void TIM8_BRK_TIM12_IRQHandler(void);
-WEAK_ALIAS void TIM8_UP_TIM13_IRQHandler(void);
-WEAK_ALIAS void TIM8_TRG_COM_TIM14_IRQHandler(void);
-WEAK_ALIAS void TIM8_CC_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream7_IRQHandler(void);
-WEAK_ALIAS void FMC_IRQHandler(void);
-WEAK_ALIAS void SDMMC1_IRQHandler(void);
-WEAK_ALIAS void TIM5_IRQHandler(void);
-WEAK_ALIAS void SPI3_IRQHandler(void);
-WEAK_ALIAS void UART4_IRQHandler(void);
-WEAK_ALIAS void UART5_IRQHandler(void);
-WEAK_ALIAS void TIM6_DAC_IRQHandler(void);
-WEAK_ALIAS void TIM7_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream0_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream1_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream2_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream3_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream4_IRQHandler(void);
-WEAK_ALIAS void ETH_IRQHandler(void);
-WEAK_ALIAS void ETH_WKUP_IRQHandler(void);
-WEAK_ALIAS void CAN2_TX_IRQHandler(void);
-WEAK_ALIAS void CAN2_RX0_IRQHandler(void);
-WEAK_ALIAS void CAN2_RX1_IRQHandler(void);
-WEAK_ALIAS void CAN2_SCE_IRQHandler(void);
-WEAK_ALIAS void OTG_FS_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream5_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream6_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream7_IRQHandler(void);
-WEAK_ALIAS void USART6_IRQHandler(void);
-WEAK_ALIAS void I2C3_EV_IRQHandler(void);
-WEAK_ALIAS void I2C3_ER_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_EP1_OUT_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_EP1_IN_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_WKUP_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_IRQHandler(void);
-WEAK_ALIAS void DCMI_IRQHandler(void);
-WEAK_ALIAS void RNG_IRQHandler(void);
-WEAK_ALIAS void FPU_IRQHandler(void);
-WEAK_ALIAS void UART7_IRQHandler(void);
-WEAK_ALIAS void UART8_IRQHandler(void);
-WEAK_ALIAS void SPI4_IRQHandler(void);
-WEAK_ALIAS void SPI5_IRQHandler(void);
-WEAK_ALIAS void SPI6_IRQHandler(void);
-WEAK_ALIAS void SAI1_IRQHandler(void);
-WEAK_ALIAS void LTDC_IRQHandler(void);
-WEAK_ALIAS void LTDC_ER_IRQHandler(void);
-WEAK_ALIAS void DMA2D_IRQHandler(void);
-
-// IRQ table
-extern void _estack();
-__attribute__((section(".vectors"))) void (*tab[16 + 91])(void) = {
-    // Cortex interrupts
-    _estack, _reset, NMI_Handler, HardFault_Handler, MemManage_Handler,
-    BusFault_Handler, UsageFault_Handler, 0, 0, 0, 0, SVC_Handler,
-    DebugMon_Handler, 0, PendSV_Handler, SysTick_Handler,
-
-    // Interrupts from peripherals
-    WWDG_IRQHandler, PVD_IRQHandler, TAMP_STAMP_IRQHandler, RTC_WKUP_IRQHandler,
-    FLASH_IRQHandler, RCC_IRQHandler, EXTI0_IRQHandler, EXTI1_IRQHandler,
-    EXTI2_IRQHandler, EXTI3_IRQHandler, EXTI4_IRQHandler,
-    DMA1_Stream0_IRQHandler, DMA1_Stream1_IRQHandler, DMA1_Stream2_IRQHandler,
-    DMA1_Stream3_IRQHandler, DMA1_Stream4_IRQHandler, DMA1_Stream5_IRQHandler,
-    DMA1_Stream6_IRQHandler, ADC_IRQHandler, CAN1_TX_IRQHandler,
-    CAN1_RX0_IRQHandler, CAN1_RX1_IRQHandler, CAN1_SCE_IRQHandler,
-    EXTI9_5_IRQHandler, TIM1_BRK_TIM9_IRQHandler, TIM1_UP_TIM10_IRQHandler,
-    TIM1_TRG_COM_TIM11_IRQHandler, TIM1_CC_IRQHandler, TIM2_IRQHandler,
-    TIM3_IRQHandler, TIM4_IRQHandler, I2C1_EV_IRQHandler, I2C1_ER_IRQHandler,
-    I2C2_EV_IRQHandler, I2C2_ER_IRQHandler, SPI1_IRQHandler, SPI2_IRQHandler,
-    USART1_IRQHandler, USART2_IRQHandler, USART3_IRQHandler,
-    EXTI15_10_IRQHandler, RTC_Alarm_IRQHandler, OTG_FS_WKUP_IRQHandler,
-    TIM8_BRK_TIM12_IRQHandler, TIM8_UP_TIM13_IRQHandler,
-    TIM8_TRG_COM_TIM14_IRQHandler, TIM8_CC_IRQHandler, DMA1_Stream7_IRQHandler,
-    FMC_IRQHandler, SDMMC1_IRQHandler, TIM5_IRQHandler, SPI3_IRQHandler,
-    UART4_IRQHandler, UART5_IRQHandler, TIM6_DAC_IRQHandler, TIM7_IRQHandler,
-    DMA2_Stream0_IRQHandler, DMA2_Stream1_IRQHandler, DMA2_Stream2_IRQHandler,
-    DMA2_Stream3_IRQHandler, DMA2_Stream4_IRQHandler, ETH_IRQHandler,
-    ETH_WKUP_IRQHandler, CAN2_TX_IRQHandler, CAN2_RX0_IRQHandler,
-    CAN2_RX1_IRQHandler, CAN2_SCE_IRQHandler, OTG_FS_IRQHandler,
-    DMA2_Stream5_IRQHandler, DMA2_Stream6_IRQHandler, DMA2_Stream7_IRQHandler,
-    USART6_IRQHandler, I2C3_EV_IRQHandler, I2C3_ER_IRQHandler,
-    OTG_HS_EP1_OUT_IRQHandler, OTG_HS_EP1_IN_IRQHandler, OTG_HS_WKUP_IRQHandler,
-    OTG_HS_IRQHandler, DCMI_IRQHandler, 0, RNG_IRQHandler, FPU_IRQHandler,
-    UART7_IRQHandler, UART8_IRQHandler, SPI4_IRQHandler, SPI5_IRQHandler,
-    SPI6_IRQHandler, SAI1_IRQHandler, LTDC_IRQHandler, LTDC_ER_IRQHandler,
-    DMA2D_IRQHandler};

examples/stm32/nucleo-f429zi-baremetal/hal.h

@@ -4,6 +4,8 @@
 
 #pragma once
 
+#include <stm32f429xx.h>
+
 #include <stdbool.h>
 #include <stdint.h>
 #include <stdio.h>
@@ -26,76 +28,18 @@ enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 180, PLL_P = 2 };  // Run at 180 Mhz
 #define APB1_FREQUENCY (SYS_FREQUENCY / (BIT(APB1_PRE - 3)))
 
 static inline void spin(volatile uint32_t count) {
-  while (count--) asm("nop");
+  while (count--) (void) 0;
 }
 
-struct rcc {
-  volatile uint32_t CR, PLLCFGR, CFGR, CIR, AHB1RSTR, AHB2RSTR, AHB3RSTR,
-      RESERVED0, APB1RSTR, APB2RSTR, RESERVED1[2], AHB1ENR, AHB2ENR, AHB3ENR,
-      RESERVED2, APB1ENR, APB2ENR, RESERVED3[2], AHB1LPENR, AHB2LPENR,
-      AHB3LPENR, RESERVED4, APB1LPENR, APB2LPENR, RESERVED5[2], BDCR, CSR,
-      RESERVED6[2], SSCGR, PLLI2SCFGR;
-};
-#define RCC ((struct rcc *) 0x40023800)
-
-struct pwr {
-  volatile uint32_t CR, CSR;
-};
-#define PWR ((struct pwr *) 0x40007000)
-
-struct nvic {
-  volatile uint32_t ISER[8], RESERVED0[24], ICER[8], RSERVED1[24], ISPR[8],
-      RESERVED2[24], ICPR[8], RESERVED3[24], IABR[8], RESERVED4[56], IP[240],
-      RESERVED5[644], STIR;
-};
-#define NVIC ((struct nvic *) 0xe000e100)
-static inline void nvic_set_prio(int irq, uint32_t prio) {
-  NVIC->IP[irq] = prio << 4;
-}
-static inline void nvic_enable_irq(int irq) {
-  NVIC->ISER[irq >> 5] = (uint32_t) (1 << (irq & 31));
-}
-
-struct systick {
-  volatile uint32_t CTRL, LOAD, VAL, CALIB;
-};
-#define SYSTICK ((struct systick *) 0xe000e010)  // 2.2.2
-static inline void systick_init(uint32_t ticks) {
-  if ((ticks - 1) > 0xffffff) return;  // Systick timer is 24 bit
-  SYSTICK->LOAD = ticks - 1;
-  SYSTICK->VAL = 0;
-  SYSTICK->CTRL = BIT(0) | BIT(1) | BIT(2);  // Enable systick
-}
-
-struct flash {
-  volatile uint32_t ACR, KEYR, OPTKEYR, SR, CR, AR, RESERVED, OBR, WRPR;
-};
-#define FLASH ((struct flash *) 0x40023c00)
-
-struct scb {
-  volatile uint32_t CPUID, ICSR, VTOR, AIRCR, SCR, CCR, SHPR[3], SHCSR, CFSR,
-      HFSR, DFSR, MMFAR, BFAR, AFSR, ID_PFR[2], ID_DFR, ID_AFR, ID_MFR[4],
-      ID_ISAR[5], RESERVED0[1], CLIDR, CTR, CCSIDR, CSSELR, CPACR,
-      RESERVED3[93], STIR, RESERVED4[15], MVFR0, MVFR1, MVFR2, RESERVED5[1],
-      ICIALLU, RESERVED6[1], ICIMVAU, DCIMVAC, DCISW, DCCMVAU, DCCMVAC, DCCSW,
-      DCCIMVAC, DCCISW, RESERVED7[6], ITCMCR, DTCMCR, AHBPCR, CACR, AHBSCR,
-      RESERVED8[1], ABFSR;
-};
-#define SCB ((struct scb *) 0xe000ed00)
-
 enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
 enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
 enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
 enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
+#define GPIO(N) ((GPIO_TypeDef *) (0x40020000 + 0x400 * (N)))
 
-struct gpio {
+static GPIO_TypeDef *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
-  volatile uint32_t MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFR[2];
-};
-#define GPIO(N) ((struct gpio *) (0x40020000 + 0x400 * (N)))
-
-static struct gpio *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
 static inline void gpio_toggle(uint16_t pin) {
-  struct gpio *gpio = gpio_bank(pin);
+  GPIO_TypeDef *gpio = gpio_bank(pin);
   uint32_t mask = BIT(PINNO(pin));
   gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
 }
@@ -103,12 +47,12 @@ static inline int gpio_read(uint16_t pin) {
   return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
 }
 static inline void gpio_write(uint16_t pin, bool val) {
-  struct gpio *gpio = gpio_bank(pin);
+  GPIO_TypeDef *gpio = gpio_bank(pin);
   gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
 }
 static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
                              uint8_t speed, uint8_t pull, uint8_t af) {
-  struct gpio *gpio = gpio_bank(pin);
+  GPIO_TypeDef *gpio = gpio_bank(pin);
   uint8_t n = (uint8_t) (PINNO(pin));
   RCC->AHB1ENR |= BIT(PINBANK(pin));  // Enable GPIO clock
   SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
@@ -127,6 +71,7 @@ static inline void gpio_output(uint16_t pin) {
             GPIO_PULL_NONE, 0);
 }
 
+#if 0
 struct syscfg {
   volatile uint32_t MEMRMP, PMC, EXTICR[4], RESERVED[2], CMPCR;
 };
@@ -136,6 +81,7 @@ struct exti {
   volatile uint32_t IMR, EMR, RTSR, FTSR, SWIER, PR;
 };
 #define EXTI ((struct exti *) 0x40013c00)
+#endif
 
 static inline void irq_exti_attach(uint16_t pin) {
   uint8_t bank = (uint8_t) (PINBANK(pin)), n = (uint8_t) (PINNO(pin));
@@ -146,22 +92,28 @@ static inline void irq_exti_attach(uint16_t pin) {
   EXTI->RTSR |= BIT(n);
   EXTI->FTSR |= BIT(n);
   int irqvec = n < 5 ? 6 + n : n < 10 ? 23 : 40;  // IRQ vector index, 10.1.2
-  nvic_set_prio(irqvec, 3);
+  NVIC_SetPriority(irqvec, 3);
-  nvic_enable_irq(irqvec);
+  NVIC_EnableIRQ(irqvec);
 }
 
-struct uart {
+#if 0
+USART_TypeDef {
   volatile uint32_t SR, DR, BRR, CR1, CR2, CR3, GTPR;
 };
-#define UART1 ((struct uart *) 0x40011000)
+#define UART1 ((USART_TypeDef *) 0x40011000)
-#define UART2 ((struct uart *) 0x40004400)
+#define UART2 ((USART_TypeDef *) 0x40004400)
-#define UART3 ((struct uart *) 0x40004800)
+#define UART3 ((USART_TypeDef *) 0x40004800)
+#endif
+
+#define UART1 USART1
+#define UART2 USART2
+#define UART3 USART3
 
 #ifndef UART_DEBUG
 #define UART_DEBUG UART3
 #endif
 
-static inline void uart_init(struct uart *uart, unsigned long baud) {
+static inline void uart_init(USART_TypeDef *uart, unsigned long baud) {
   // https://www.st.com/resource/en/datasheet/stm32f429zi.pdf
   uint8_t af = 7;           // Alternate function
   uint16_t rx = 0, tx = 0;  // pins
@@ -181,17 +133,17 @@ static inline void uart_init(struct uart *uart, unsigned long baud) {
   uart->BRR = freq / baud;                 // Set baud rate
   uart->CR1 |= BIT(13) | BIT(2) | BIT(3);  // Set UE, RE, TE
 }
-static inline void uart_write_byte(struct uart *uart, uint8_t byte) {
+static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
   uart->DR = byte;
   while ((uart->SR & BIT(7)) == 0) spin(1);
 }
-static inline void uart_write_buf(struct uart *uart, char *buf, size_t len) {
+static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
   while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
 }
-static inline int uart_read_ready(struct uart *uart) {
+static inline int uart_read_ready(USART_TypeDef *uart) {
   return uart->SR & BIT(5);  // If RXNE bit is set, data is ready
 }
-static inline uint8_t uart_read_byte(struct uart *uart) {
+static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
   return (uint8_t) (uart->DR & 255);
 }
 
@@ -199,9 +151,8 @@ static inline void clock_init(void) {                 // Set clock frequency
   SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));  // Enable FPU
   asm("DSB");
   asm("ISB");
-  FLASH->ACR |= FLASH_LATENCY | BIT(8) |
+  FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9);    // Flash latency
-                BIT(9);              // Flash latency, prefetch, Icache, Dcache
+  RCC->PLLCFGR &= ~((BIT(17) - 1));                 // Clear PLL multipliers
-  RCC->PLLCFGR &= ~((BIT(17) - 1));  // Clear PLL multipliers
   RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16;    // Set PLL_P
   RCC->PLLCFGR |= PLL_M | (PLL_N << 6);             // Set PLL_M and PLL_N
   RCC->CR |= BIT(24);                               // Enable PLL

examples/stm32/nucleo-f429zi-baremetal/link.ld

@@ -1,14 +1,14 @@
-ENTRY(_reset);
+ENTRY(Reset_Handler);
 MEMORY {
-  flash(rx)  : ORIGIN = 0x08000000, LENGTH = 2048k
+  flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
   sram(rwx) : ORIGIN = 0x20000000, LENGTH = 192k  /* remaining 64k in a separate address space */
 }
 _estack     = ORIGIN(sram) + LENGTH(sram);    /* stack points to end of SRAM */
 
 SECTIONS {
-  .vectors  : { KEEP(*(.vectors)) }   > flash
+  .vectors  : { KEEP(*(.isr_vector)) }  > flash
-  .text     : { *(.text*) }           > flash
+  .text     : { *(.text* .text.*) }     > flash
-  .rodata   : { *(.rodata*) }         > flash
+  .rodata   : { *(.rodata*) }           > flash
 
   .data : {
     _sdata = .;   /* for init_ram() */

examples/stm32/nucleo-f429zi-baremetal/main.c

@@ -1,7 +1,7 @@
-// Copyright (c) 2022 Cesanta Software Limited
+// Copyright (c) 2022-2023 Cesanta Software Limited
 // All rights reserved
 
-#include "mcu.h"
+#include "hal.h"
 #include "mongoose.h"
 
 #define LED1 PIN('B', 0)      // On-board LED pin (green)
@@ -31,20 +31,23 @@ void EXTI15_10_IRQHandler(void) {  // External interrupt handler
   gpio_write(LED1, gpio_read(BTN1));  // No debounce. Turn LED if button pressed
 }
 
-static void timer_cb(void *arg) {
+void SystemInit(void) {                  // Called automatically by startup code
+  clock_init();                          // Set clock to 180MHz
+  SysTick_Config(SYS_FREQUENCY / 1000);  // Increment s_ticks every ms
+}
+
+static void timer_fn(void *arg) {
   gpio_toggle(LED2);  // Blink LED
   bool up = ((struct mip_if *) arg)->state == MIP_STATE_READY;
   MG_INFO(("Ethernet: %s", up ? "up" : "down"));  // Show network status
 }
 
 int main(void) {
-  clock_init();                        // Set clock to 180MHz
+  gpio_output(LED1);              // Setup green LED
-  systick_init(SYS_FREQUENCY / 1000);  // Increment s_ticks every ms
+  gpio_output(LED2);              // Setup blue LED
-  gpio_output(LED1);                   // Setup green LED
+  gpio_input(BTN1);               // Set button to input
-  gpio_output(LED2);                   // Setup blue LED
+  irq_exti_attach(BTN1);          // Attach BTN1 to exti
-  gpio_input(BTN1);                    // Set button to input
+  uart_init(UART_DEBUG, 115200);  // Initialise debug printf
-  irq_exti_attach(BTN1);               // Attach BTN1 to exti
-  uart_init(UART_DEBUG, 115200);       // Initialise debug printf
 
   MG_INFO(("Starting, CPU freq %g MHz", (double) SYS_FREQUENCY / 1000000));
 
@@ -57,7 +60,7 @@ int main(void) {
     gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
               GPIO_PULL_NONE, 11);
   }
-  nvic_enable_irq(61);                          // Setup Ethernet IRQ handler
+  NVIC_EnableIRQ(ETH_IRQn);                     // Setup Ethernet IRQ handler
   RCC->APB2ENR |= BIT(14);                      // Enable SYSCFG
   SYSCFG->PMC |= BIT(23);                       // Use RMII. Goes first!
   RCC->AHB1ENR |= BIT(25) | BIT(26) | BIT(27);  // Enable Ethernet clocks
@@ -76,7 +79,7 @@ int main(void) {
                        .driver = &mip_driver_stm32,
                        .driver_data = &driver_data};
   mip_init(&mgr, &mif);
-  mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_cb, &mif);
+  mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
 
   MG_INFO(("Waiting until network is up..."));
   while (mif.state != MIP_STATE_READY) {

examples/stm32/nucleo-f429zi-baremetal/syscalls.c

@@ -1,6 +1,6 @@
 #include <sys/stat.h>
 
-#include "mcu.h"
+#include "hal.h"
 
 int _fstat(int fd, struct stat *st) {
   if (fd < 0) return -1;
@@ -81,3 +81,5 @@ int mkdir(const char *path, mode_t mode) {
   (void) path, (void) mode;
   return -1;
 }
+
+void _init(void) {}

examples/stm32/nucleo-f746zg-baremetal/Makefile

@@ -1,37 +1,60 @@
-TARGET  = firmware
+# Download CMSIS header files from Github on demand
-CFLAGS  ?=  -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \
+CMSIS_CORE_VERSION ?= 5.9.0      # ARM Cortex-M definitions
-            -Wformat-truncation -fno-common -Wconversion \
+CMSIS_CORE_REPO ?= https://github.com/ARM-software/CMSIS_5
-            -g3 -Os -ffunction-sections -fdata-sections -I. \
+CMSIS_DEVICE_VERSION ?= v1.2.8   # ST MCU peripheral definitions
-            -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 $(EXTRA_CFLAGS)
+CMSIS_DEVICE_REPO ?= https://github.com/STMicroelectronics/cmsis_device_f7
-LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
-SOURCES = boot.c main.c syscalls.c
 
-# Add Mongoose-specific flags and source files
+CFLAGS ?= -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \
+          -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion\
+          -g3 -Os -ffunction-sections -fdata-sections \
+          -I . -I cmsis_core/CMSIS/Core/Include -I cmsis_device_f7/Include \
+          -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 $(EXTRA_CFLAGS)
+LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
+SOURCES = main.c syscalls.c cmsis_device_f7/Source/Templates/gcc/startup_stm32f746xx.s
+
+# Mongoose-specific build flags and source code files
+# Build options reference: https://mongoose.ws/documentation/#build-options
 CFLAGS  += -I../../.. -DMG_ARCH=MG_ARCH_NEWLIB -DMG_ENABLE_CUSTOM_MILLIS=1 -DMG_ENABLE_MIP=1 -DMG_ENABLE_PACKED_FS=1
 SOURCES += ../../../mongoose.c ../../device-dashboard/net.c ../../device-dashboard/packed_fs.c
 
-all build example: $(TARGET).bin
+# Build flashable .bin file
+all build example: firmware.bin
 
-$(TARGET).bin: $(TARGET).elf
+# .bin file is made from .elf file, by concatenating .text and .data sections
+firmware.bin: firmware.elf
 	arm-none-eabi-objcopy -O binary $< $@
 
-$(TARGET).elf: $(SOURCES) mcu.h
+# .elf file is produced by compiling sources
+firmware.elf: $(SOURCES) hal.h link.ld cmsis_core cmsis_device_f7
 	arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
 
-# Note: on "unknown chip id" flash error, wire BOOT0 to VDD and st-flash erase
+# Flash .bin file to the target board via the built-in debugger
-flash: $(TARGET).bin
+flash: firmware.bin
-	st-flash --reset write $(TARGET).bin 0x8000000
+	st-flash --reset write $< 0x8000000
+
+# Download ST's CMSIS headers with peripheral definitions
+cmsis_device_f7/Source/Templates/gcc/startup_stm32f746xx.s: cmsis_device_f7
+cmsis_device_f7:
+	git clone --depth 1 -b $(CMSIS_DEVICE_VERSION) $(CMSIS_DEVICE_REPO) $@
+
+# Download ARM's CMSIS headers with core Cortex-M definitions
+cmsis_core:
+	git clone --depth 1 -b $(CMSIS_CORE_VERSION) $(CMSIS_CORE_REPO) $@
 
 # Requires env variable VCON_API_KEY set
 DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/5
-test:	EXTRA_CFLAGS += -DUART_DEBUG=UART1
-test:	update
-	curl --fail -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
-	grep 'READY, IP:' /tmp/output.txt
-	grep 'MQTT connected' /tmp/output.txt
 
-update: $(TARGET).bin
+# Upload firmware to a remote test device
+update: firmware.bin
 	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
 
+# Read serial port on a remote test device for 5 seconds, store in a
+# temporary file, and check the output for expected patterns
+test:	EXTRA_CFLAGS += -DUART_DEBUG=UART1
+test: update
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
+	grep 'READY, IP:' /tmp/output.txt       # Check for network init
+	grep 'MQTT connected' /tmp/output.txt   # Check for MQTT connection success
+
 clean:
-	@rm -rf $(TARGET).* *.su
+	@rm -rf firmware.* *.su cmsis_core cmsis_device_f7

examples/stm32/nucleo-f746zg-baremetal/boot.c

@@ -1,169 +0,0 @@
-// Copyright (c) 2022 Cesanta Software Limited
-// All rights reserved
-
-// Startup code
-__attribute__((naked, noreturn)) void _reset(void) {
-  // Initialise memory
-  extern long _sbss, _ebss, _sdata, _edata, _sidata;
-  for (long *src = &_sbss; src < &_ebss; src++) *src = 0;
-  for (long *src = &_sdata, *dst = &_sidata; src < &_edata;) *src++ = *dst++;
-
-  // Call main()
-  extern void main(void);
-  main();
-  for (;;) (void) 0;
-}
-
-void __attribute__((weak)) DefaultIRQHandler(void) {
-  for (;;) (void) 0;
-}
-
-#define WEAK_ALIAS __attribute__((weak, alias("DefaultIRQHandler")))
-
-WEAK_ALIAS void NMI_Handler(void);
-WEAK_ALIAS void HardFault_Handler(void);
-WEAK_ALIAS void MemManage_Handler(void);
-WEAK_ALIAS void BusFault_Handler(void);
-WEAK_ALIAS void UsageFault_Handler(void);
-WEAK_ALIAS void SVC_Handler(void);
-WEAK_ALIAS void DebugMon_Handler(void);
-WEAK_ALIAS void PendSV_Handler(void);
-WEAK_ALIAS void SysTick_Handler(void);
-
-WEAK_ALIAS void WWDG_IRQHandler(void);
-WEAK_ALIAS void PVD_IRQHandler(void);
-WEAK_ALIAS void TAMP_STAMP_IRQHandler(void);
-WEAK_ALIAS void RTC_WKUP_IRQHandler(void);
-WEAK_ALIAS void FLASH_IRQHandler(void);
-WEAK_ALIAS void RCC_IRQHandler(void);
-WEAK_ALIAS void EXTI0_IRQHandler(void);
-WEAK_ALIAS void EXTI1_IRQHandler(void);
-WEAK_ALIAS void EXTI2_IRQHandler(void);
-WEAK_ALIAS void EXTI3_IRQHandler(void);
-WEAK_ALIAS void EXTI4_IRQHandler(void);
-WEAK_ALIAS void EXTI9_5_IRQHandler(void);
-WEAK_ALIAS void EXTI15_10_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream0_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream1_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream2_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream3_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream4_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream5_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream6_IRQHandler(void);
-WEAK_ALIAS void ADC_IRQHandler(void);
-WEAK_ALIAS void CAN1_TX_IRQHandler(void);
-WEAK_ALIAS void CAN1_RX0_IRQHandler(void);
-WEAK_ALIAS void CAN1_RX1_IRQHandler(void);
-WEAK_ALIAS void CAN1_SCE_IRQHandler(void);
-WEAK_ALIAS void TIM1_BRK_TIM9_IRQHandler(void);
-WEAK_ALIAS void TIM1_UP_TIM10_IRQHandler(void);
-WEAK_ALIAS void TIM1_TRG_COM_TIM11_IRQHandler(void);
-WEAK_ALIAS void TIM1_CC_IRQHandler(void);
-WEAK_ALIAS void TIM2_IRQHandler(void);
-WEAK_ALIAS void TIM3_IRQHandler(void);
-WEAK_ALIAS void TIM4_IRQHandler(void);
-WEAK_ALIAS void I2C1_EV_IRQHandler(void);
-WEAK_ALIAS void I2C1_ER_IRQHandler(void);
-WEAK_ALIAS void I2C2_EV_IRQHandler(void);
-WEAK_ALIAS void I2C2_ER_IRQHandler(void);
-WEAK_ALIAS void SPI1_IRQHandler(void);
-WEAK_ALIAS void SPI2_IRQHandler(void);
-WEAK_ALIAS void USART1_IRQHandler(void);
-WEAK_ALIAS void USART2_IRQHandler(void);
-WEAK_ALIAS void USART3_IRQHandler(void);
-WEAK_ALIAS void RTC_Alarm_IRQHandler(void);
-WEAK_ALIAS void OTG_FS_WKUP_IRQHandler(void);
-WEAK_ALIAS void TIM8_BRK_TIM12_IRQHandler(void);
-WEAK_ALIAS void TIM8_UP_TIM13_IRQHandler(void);
-WEAK_ALIAS void TIM8_TRG_COM_TIM14_IRQHandler(void);
-WEAK_ALIAS void TIM8_CC_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream7_IRQHandler(void);
-WEAK_ALIAS void FMC_IRQHandler(void);
-WEAK_ALIAS void SDMMC1_IRQHandler(void);
-WEAK_ALIAS void TIM5_IRQHandler(void);
-WEAK_ALIAS void SPI3_IRQHandler(void);
-WEAK_ALIAS void UART4_IRQHandler(void);
-WEAK_ALIAS void UART5_IRQHandler(void);
-WEAK_ALIAS void TIM6_DAC_IRQHandler(void);
-WEAK_ALIAS void TIM7_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream0_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream1_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream2_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream3_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream4_IRQHandler(void);
-WEAK_ALIAS void ETH_IRQHandler(void);
-WEAK_ALIAS void ETH_WKUP_IRQHandler(void);
-WEAK_ALIAS void CAN2_TX_IRQHandler(void);
-WEAK_ALIAS void CAN2_RX0_IRQHandler(void);
-WEAK_ALIAS void CAN2_RX1_IRQHandler(void);
-WEAK_ALIAS void CAN2_SCE_IRQHandler(void);
-WEAK_ALIAS void OTG_FS_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream5_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream6_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream7_IRQHandler(void);
-WEAK_ALIAS void USART6_IRQHandler(void);
-WEAK_ALIAS void I2C3_EV_IRQHandler(void);
-WEAK_ALIAS void I2C3_ER_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_EP1_OUT_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_EP1_IN_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_WKUP_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_IRQHandler(void);
-WEAK_ALIAS void DCMI_IRQHandler(void);
-WEAK_ALIAS void RNG_IRQHandler(void);
-WEAK_ALIAS void FPU_IRQHandler(void);
-WEAK_ALIAS void UART7_IRQHandler(void);
-WEAK_ALIAS void UART8_IRQHandler(void);
-WEAK_ALIAS void SPI4_IRQHandler(void);
-WEAK_ALIAS void SPI5_IRQHandler(void);
-WEAK_ALIAS void SPI6_IRQHandler(void);
-WEAK_ALIAS void SAI1_IRQHandler(void);
-WEAK_ALIAS void LTDC_IRQHandler(void);
-WEAK_ALIAS void LTDC_ER_IRQHandler(void);
-WEAK_ALIAS void DMA2D_IRQHandler(void);
-WEAK_ALIAS void SAI2_IRQHandler(void);
-WEAK_ALIAS void QUADSPI_IRQHandler(void);
-WEAK_ALIAS void LPTIM1_IRQHandler(void);
-WEAK_ALIAS void CEC_IRQHandler(void);
-WEAK_ALIAS void I2C4_EV_IRQHandler(void);
-WEAK_ALIAS void I2C4_ER_IRQHandler(void);
-WEAK_ALIAS void SPDIF_RX_IRQHandler(void);
-
-// IRQ table
-extern void _estack();
-__attribute__((section(".vectors"))) void (*tab[16 + 98])(void) = {
-    // Cortex interrupts
-    _estack, _reset, NMI_Handler, HardFault_Handler, MemManage_Handler,
-    BusFault_Handler, UsageFault_Handler, 0, 0, 0, 0, SVC_Handler,
-    DebugMon_Handler, 0, PendSV_Handler, SysTick_Handler,
-
-    // Interrupts from peripherals
-    WWDG_IRQHandler, PVD_IRQHandler, TAMP_STAMP_IRQHandler, RTC_WKUP_IRQHandler,
-    FLASH_IRQHandler, RCC_IRQHandler, EXTI0_IRQHandler, EXTI1_IRQHandler,
-    EXTI2_IRQHandler, EXTI3_IRQHandler, EXTI4_IRQHandler,
-    DMA1_Stream0_IRQHandler, DMA1_Stream1_IRQHandler, DMA1_Stream2_IRQHandler,
-    DMA1_Stream3_IRQHandler, DMA1_Stream4_IRQHandler, DMA1_Stream5_IRQHandler,
-    DMA1_Stream6_IRQHandler, ADC_IRQHandler, CAN1_TX_IRQHandler,
-    CAN1_RX0_IRQHandler, CAN1_RX1_IRQHandler, CAN1_SCE_IRQHandler,
-    EXTI9_5_IRQHandler, TIM1_BRK_TIM9_IRQHandler, TIM1_UP_TIM10_IRQHandler,
-    TIM1_TRG_COM_TIM11_IRQHandler, TIM1_CC_IRQHandler, TIM2_IRQHandler,
-    TIM3_IRQHandler, TIM4_IRQHandler, I2C1_EV_IRQHandler, I2C1_ER_IRQHandler,
-    I2C2_EV_IRQHandler, I2C2_ER_IRQHandler, SPI1_IRQHandler, SPI2_IRQHandler,
-    USART1_IRQHandler, USART2_IRQHandler, USART3_IRQHandler,
-    EXTI15_10_IRQHandler, RTC_Alarm_IRQHandler, OTG_FS_WKUP_IRQHandler,
-    TIM8_BRK_TIM12_IRQHandler, TIM8_UP_TIM13_IRQHandler,
-    TIM8_TRG_COM_TIM14_IRQHandler, TIM8_CC_IRQHandler, DMA1_Stream7_IRQHandler,
-    FMC_IRQHandler, SDMMC1_IRQHandler, TIM5_IRQHandler, SPI3_IRQHandler,
-    UART4_IRQHandler, UART5_IRQHandler, TIM6_DAC_IRQHandler, TIM7_IRQHandler,
-    DMA2_Stream0_IRQHandler, DMA2_Stream1_IRQHandler, DMA2_Stream2_IRQHandler,
-    DMA2_Stream3_IRQHandler, DMA2_Stream4_IRQHandler, ETH_IRQHandler,
-    ETH_WKUP_IRQHandler, CAN2_TX_IRQHandler, CAN2_RX0_IRQHandler,
-    CAN2_RX1_IRQHandler, CAN2_SCE_IRQHandler, OTG_FS_IRQHandler,
-    DMA2_Stream5_IRQHandler, DMA2_Stream6_IRQHandler, DMA2_Stream7_IRQHandler,
-    USART6_IRQHandler, I2C3_EV_IRQHandler, I2C3_ER_IRQHandler,
-    OTG_HS_EP1_OUT_IRQHandler, OTG_HS_EP1_IN_IRQHandler, OTG_HS_WKUP_IRQHandler,
-    OTG_HS_IRQHandler, DCMI_IRQHandler, 0, RNG_IRQHandler, FPU_IRQHandler,
-    UART7_IRQHandler, UART8_IRQHandler, SPI4_IRQHandler, SPI5_IRQHandler,
-    SPI6_IRQHandler, SAI1_IRQHandler, LTDC_IRQHandler, LTDC_ER_IRQHandler,
-    DMA2D_IRQHandler, SAI2_IRQHandler, QUADSPI_IRQHandler, LPTIM1_IRQHandler,
-    CEC_IRQHandler, I2C4_EV_IRQHandler, I2C4_ER_IRQHandler,
-    SPDIF_RX_IRQHandler};

examples/stm32/nucleo-f746zg-baremetal/hal.h

@@ -4,6 +4,8 @@
 
 #pragma once
 
+#include <stm32f746xx.h>
+
 #include <stdbool.h>
 #include <stdint.h>
 #include <stdio.h>
@@ -18,85 +20,28 @@
 /* System clock
 5.3.3: APB1 clock <= 54MHz; APB2 clock <= 108MHz
 3.3.2, Table 5: configure flash latency (WS) in accordance to clock freq
-38.4: The AHB clock frequency must be at least 25 MHz when the Ethernet controller is used */
+38.4: The AHB clock frequency must be at least 25 MHz when the Ethernet
+controller is used */
 enum { APB1_PRE = 5 /* AHB clock / 4 */, APB2_PRE = 4 /* AHB clock / 2 */ };
 enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 216, PLL_P = 2 };  // Run at 216 Mhz
-#define FLASH_LATENCY 7 
+#define FLASH_LATENCY 7
 #define SYS_FREQUENCY ((PLL_HSI * PLL_N / PLL_M / PLL_P) * 1000000)
 #define APB2_FREQUENCY (SYS_FREQUENCY / (BIT(APB2_PRE - 3)))
 #define APB1_FREQUENCY (SYS_FREQUENCY / (BIT(APB1_PRE - 3)))
 
 static inline void spin(volatile uint32_t count) {
-  while (count--) asm("nop");
+  while (count--) (void) 0;
 }
 
-struct rcc {
-  volatile uint32_t CR, PLLCFGR, CFGR, CIR, AHB1RSTR, AHB2RSTR, AHB3RSTR,
-      RESERVED0, APB1RSTR, APB2RSTR, RESERVED1[2], AHB1ENR, AHB2ENR, AHB3ENR,
-      RESERVED2, APB1ENR, APB2ENR, RESERVED3[2], AHB1LPENR, AHB2LPENR,
-      AHB3LPENR, RESERVED4, APB1LPENR, APB2LPENR, RESERVED5[2], BDCR, CSR,
-      RESERVED6[2], SSCGR, PLLI2SCFGR, PLLSAICFGR, DCKCFGR1, DCKCFGR2;
-};
-#define RCC ((struct rcc *) 0x40023800)
-
-struct pwr {
-  volatile uint32_t CR1, CSR1, CR2, CSR2;
-};
-#define PWR ((struct pwr *) 0x40007000)
-
-struct nvic {
-  volatile uint32_t ISER[8], RESERVED0[24], ICER[8], RSERVED1[24], ISPR[8],
-      RESERVED2[24], ICPR[8], RESERVED3[24], IABR[8], RESERVED4[56], IP[240],
-      RESERVED5[644], STIR;
-};
-#define NVIC ((struct nvic *) 0xe000e100)
-static inline void nvic_set_prio(int irq, uint32_t prio) {
-  NVIC->IP[irq] = prio << 4;
-}
-static inline void nvic_enable_irq(int irq) {
-  NVIC->ISER[irq >> 5] = (uint32_t) (1 << (irq & 31));
-}
-
-struct systick {
-  volatile uint32_t CTRL, LOAD, VAL, CALIB;
-};
-#define SYSTICK ((struct systick *) 0xe000e010)  // 2.2.2
-static inline void systick_init(uint32_t ticks) {
-  if ((ticks - 1) > 0xffffff) return;  // Systick timer is 24 bit
-  SYSTICK->LOAD = ticks - 1;
-  SYSTICK->VAL = 0;
-  SYSTICK->CTRL = BIT(0) | BIT(1) | BIT(2);  // Enable systick
-}
-
-struct flash {
-  volatile uint32_t ACR, KEYR, OPTKEYR, SR, CR, AR, RESERVED, OBR, WRPR;
-};
-#define FLASH ((struct flash *) 0x40023c00)
-
-struct scb {
-  volatile uint32_t CPUID, ICSR, VTOR, AIRCR, SCR, CCR, SHPR[3], SHCSR, CFSR,
-      HFSR, DFSR, MMFAR, BFAR, AFSR, ID_PFR[2], ID_DFR, ID_AFR, ID_MFR[4],
-      ID_ISAR[5], RESERVED0[1], CLIDR, CTR, CCSIDR, CSSELR, CPACR,
-      RESERVED3[93], STIR, RESERVED4[15], MVFR0, MVFR1, MVFR2, RESERVED5[1],
-      ICIALLU, RESERVED6[1], ICIMVAU, DCIMVAC, DCISW, DCCMVAU, DCCMVAC, DCCSW,
-      DCCIMVAC, DCCISW, RESERVED7[6], ITCMCR, DTCMCR, AHBPCR, CACR, AHBSCR,
-      RESERVED8[1], ABFSR;
-};
-#define SCB ((struct scb *) 0xe000ed00)
-
 enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
 enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
 enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
 enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
+#define GPIO(N) ((GPIO_TypeDef *) (0x40020000 + 0x400 * (N)))
 
-struct gpio {
+static GPIO_TypeDef *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
-  volatile uint32_t MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFR[2];
-};
-#define GPIO(N) ((struct gpio *) (0x40020000 + 0x400 * (N)))
-
-static struct gpio *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
 static inline void gpio_toggle(uint16_t pin) {
-  struct gpio *gpio = gpio_bank(pin);
+  GPIO_TypeDef *gpio = gpio_bank(pin);
   uint32_t mask = BIT(PINNO(pin));
   gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
 }
@@ -104,12 +49,12 @@ static inline int gpio_read(uint16_t pin) {
   return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
 }
 static inline void gpio_write(uint16_t pin, bool val) {
-  struct gpio *gpio = gpio_bank(pin);
+  GPIO_TypeDef *gpio = gpio_bank(pin);
   gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
 }
 static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
                              uint8_t speed, uint8_t pull, uint8_t af) {
-  struct gpio *gpio = gpio_bank(pin);
+  GPIO_TypeDef *gpio = gpio_bank(pin);
   uint8_t n = (uint8_t) (PINNO(pin));
   RCC->AHB1ENR |= BIT(PINBANK(pin));  // Enable GPIO clock
   SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
@@ -128,16 +73,6 @@ static inline void gpio_output(uint16_t pin) {
             GPIO_PULL_NONE, 0);
 }
 
-struct syscfg {
-  volatile uint32_t MEMRMP, PMC, EXTICR[4], RESERVED[2], CMPCR;
-};
-#define SYSCFG ((struct syscfg *) 0x40013800)
-
-struct exti {
-  volatile uint32_t IMR, EMR, RTSR, FTSR, SWIER, PR;
-};
-#define EXTI ((struct exti *) 0x40013c00)
-
 static inline void irq_exti_attach(uint16_t pin) {
   uint8_t bank = (uint8_t) (PINBANK(pin)), n = (uint8_t) (PINNO(pin));
   RCC->APB2ENR |= BIT(14);  // Enable SYSCFG
@@ -147,22 +82,19 @@ static inline void irq_exti_attach(uint16_t pin) {
   EXTI->RTSR |= BIT(n);
   EXTI->FTSR |= BIT(n);
   int irqvec = n < 5 ? 6 + n : n < 10 ? 23 : 40;  // IRQ vector index, 10.1.2
-  nvic_set_prio(irqvec, 3);
+  NVIC_SetPriority(irqvec, 3);
-  nvic_enable_irq(irqvec);
+  NVIC_EnableIRQ(irqvec);
 }
 
-struct uart {
+#define UART1 USART1
-  volatile uint32_t CR1, CR2, CR3, BRR, GTPR, RTOR, RQR, ISR, ICR, RDR, TDR;
+#define UART2 USART2
-};
+#define UART3 USART3
-#define UART1 ((struct uart *) 0x40011000)
-#define UART2 ((struct uart *) 0x40004400)
-#define UART3 ((struct uart *) 0x40004800)
 
 #ifndef UART_DEBUG
 #define UART_DEBUG UART3
 #endif
 
-static inline void uart_init(struct uart *uart, unsigned long baud) {
+static inline void uart_init(USART_TypeDef *uart, unsigned long baud) {
   // https://www.st.com/resource/en/datasheet/stm32f746zg.pdf
   uint8_t af = 7;           // Alternate function
   uint16_t rx = 0, tx = 0;  // pins
@@ -179,20 +111,20 @@ static inline void uart_init(struct uart *uart, unsigned long baud) {
   gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
   gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
   uart->CR1 = 0;                          // Disable this UART
-  uart->BRR = freq / baud;                 // Set baud rate
+  uart->BRR = freq / baud;                // Set baud rate
   uart->CR1 |= BIT(0) | BIT(2) | BIT(3);  // Set UE, RE, TE
 }
-static inline void uart_write_byte(struct uart *uart, uint8_t byte) {
+static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
   uart->TDR = byte;
   while ((uart->ISR & BIT(7)) == 0) spin(1);
 }
-static inline void uart_write_buf(struct uart *uart, char *buf, size_t len) {
+static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
   while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
 }
-static inline int uart_read_ready(struct uart *uart) {
+static inline int uart_read_ready(USART_TypeDef *uart) {
   return uart->ISR & BIT(5);  // If RXNE bit is set, data is ready
 }
-static inline uint8_t uart_read_byte(struct uart *uart) {
+static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
   return (uint8_t) (uart->RDR & 255);
 }
 
@@ -206,8 +138,8 @@ static inline void clock_init(void) {  // Set clock frequency
   while ((PWR->CSR1 & BIT(17)) == 0) spin(1);  // Wait until done
 #endif
   SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));  // Enable FPU
-  asm ("DSB");
+  asm("DSB");
-  asm ("ISB");
+  asm("ISB");
   FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9);    // Flash latency, prefetch
   RCC->PLLCFGR &= ~((BIT(17) - 1));                 // Clear PLL multipliers
   RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16;    // Set PLL_P

examples/stm32/nucleo-f746zg-baremetal/link.ld

@@ -1,14 +1,14 @@
-ENTRY(_reset);
+ENTRY(Reset_Handler);
 MEMORY {
-  flash(rx)  : ORIGIN = 0x08000000, LENGTH = 1024k
+  flash(rx) : ORIGIN = 0x08000000, LENGTH = 1024k
   sram(rwx) : ORIGIN = 0x20000000, LENGTH = 320k
 }
 _estack     = ORIGIN(sram) + LENGTH(sram);    /* stack points to end of SRAM */
 
 SECTIONS {
-  .vectors  : { KEEP(*(.vectors)) }   > flash
+  .vectors  : { KEEP(*(.isr_vector)) }  > flash
-  .text     : { *(.text*) }           > flash
+  .text     : { *(.text* .text.*) }     > flash
-  .rodata   : { *(.rodata*) }         > flash
+  .rodata   : { *(.rodata*) }           > flash
 
   .data : {
     _sdata = .;   /* for init_ram() */

examples/stm32/nucleo-f746zg-baremetal/main.c

@@ -1,21 +1,17 @@
-// Copyright (c) 2022 Cesanta Software Limited
+// Copyright (c) 2022-2023 Cesanta Software Limited
 // All rights reserved
 
-#include "mcu.h"
+#include "hal.h"
 #include "mongoose.h"
 
-#define LED1 PIN('B', 0)   // On-board LED pin (green)
+#define LED1 PIN('B', 0)      // On-board LED pin (green)
-#define LED2 PIN('B', 7)   // On-board LED pin (blue)
+#define LED2 PIN('B', 7)      // On-board LED pin (blue)
-#define LED3 PIN('B', 14)  // On-board LED pin (red)
+#define LED3 PIN('B', 14)     // On-board LED pin (red)
-#define BTN1 PIN('C', 13)  // On-board user button
+#define BTN1 PIN('C', 13)     // On-board user button
+#define BLINK_PERIOD_MS 1000  // LED blinking period in millis
 
 static uint64_t s_ticks, s_exti;  // Counters, increased by IRQ handlers
 
-static void blink_cb(void *arg) {  // Blink periodically
-  gpio_toggle(LED2);
-  (void) arg;
-}
-
 uint64_t mg_millis(void) {  // Declare our own uptime function
   return s_ticks;           // Return number of milliseconds since boot
 }
@@ -35,15 +31,25 @@ void EXTI15_10_IRQHandler(void) {  // External interrupt handler
   gpio_write(LED1, gpio_read(BTN1));  // No debounce. Turn LED if button pressed
 }
 
+void SystemInit(void) {                  // Called automatically by startup code
+  clock_init();                          // Set clock to 180MHz
+  SysTick_Config(SYS_FREQUENCY / 1000);  // Increment s_ticks every ms
+}
+
+static void timer_fn(void *arg) {
+  gpio_toggle(LED2);  // Blink LED
+  bool up = ((struct mip_if *) arg)->state == MIP_STATE_READY;
+  MG_INFO(("Ethernet: %s", up ? "up" : "down"));  // Show network status
+}
+
 int main(void) {
-  static struct uart *uart = UART_DEBUG;  // Use UART3 - its attached to debug
+  gpio_output(LED1);              // Setup green LED
-  clock_init();                           // Set clock to 216MHz
+  gpio_output(LED2);              // Setup blue LED
-  systick_init(SYS_FREQUENCY / 1000);     // Increment s_ticks every ms
+  gpio_input(BTN1);               // Set button to input
-  gpio_output(LED1);                      // Setup green LED
+  irq_exti_attach(BTN1);          // Attach BTN1 to exti
-  gpio_output(LED2);                      // Setup blue LED
+  uart_init(UART_DEBUG, 115200);  // Initialise debug printf
-  gpio_input(BTN1);                       // Set button to input
+
-  irq_exti_attach(BTN1);                  // Attach BTN1 to exti
+  MG_INFO(("Starting, CPU freq %g MHz", (double) SYS_FREQUENCY / 1000000));
-  uart_init(uart, 115200);                // It is wired to the debug port
 
   // Initialise Ethernet. Enable MAC GPIO pins, see
   // https://www.farnell.com/datasheets/2014265.pdf section 6.10
@@ -54,7 +60,7 @@ int main(void) {
     gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
               GPIO_PULL_NONE, 11);
   }
-  nvic_enable_irq(61);                          // Setup Ethernet IRQ handler
+  NVIC_EnableIRQ(ETH_IRQn);                     // Setup Ethernet IRQ handler
   RCC->APB2ENR |= BIT(14);                      // Enable SYSCFG
   SYSCFG->PMC |= BIT(23);                       // Use RMII. Goes first!
   RCC->AHB1ENR |= BIT(25) | BIT(26) | BIT(27);  // Enable Ethernet clocks
@@ -64,19 +70,16 @@ int main(void) {
   struct mg_mgr mgr;        // Initialise Mongoose event manager
   mg_mgr_init(&mgr);        // and attach it to the MIP interface
   mg_log_set(MG_LL_DEBUG);  // Set log level
-  mg_timer_add(&mgr, 500, MG_TIMER_REPEAT, blink_cb, &mgr);
 
   // Initialise Mongoose network stack
   // Specify MAC address, and IP/mask/GW in network byte order for static
   // IP configuration. If IP/mask/GW are unset, DHCP is going to be used
-  struct mip_driver_stm32_data driver_data = {.mdc_cr =
+  struct mip_driver_stm32_data driver_data = {.mdc_cr = 4};  // driver_stm32.h
-                                                  4};  // See driver_stm32.h
+  struct mip_if mif = {.mac = {2, 0, 1, 2, 3, 5},
-  struct mip_if mif = {
+                       .driver = &mip_driver_stm32,
-      .mac = {2, 0, 1, 2, 3, 5},
+                       .driver_data = &driver_data};
-      .driver = &mip_driver_stm32,
-      .driver_data = &driver_data,
-  };
   mip_init(&mgr, &mif);
+  mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
 
   MG_INFO(("Waiting until network is up..."));
   while (mif.state != MIP_STATE_READY) {
@@ -88,7 +91,9 @@ int main(void) {
   mg_http_listen(&mgr, "http://0.0.0.0", device_dashboard_fn, NULL);
 
   MG_INFO(("Starting event loop"));
-  for (;;) mg_mgr_poll(&mgr, 0);  // Infinite event loop
+  for (;;) {
+    mg_mgr_poll(&mgr, 0);
+  }
 
   return 0;
 }

examples/stm32/nucleo-f746zg-baremetal/syscalls.c

@@ -1,6 +1,6 @@
 #include <sys/stat.h>
 
-#include "mcu.h"
+#include "hal.h"
 
 int _fstat(int fd, struct stat *st) {
   if (fd < 0) return -1;
@@ -81,3 +81,5 @@ int mkdir(const char *path, mode_t mode) {
   (void) path, (void) mode;
   return -1;
 }
+
+void _init(void) {}