mirror of
https://github.com/cesanta/mongoose.git
synced 2024-11-27 12:49:01 +08:00
pilot move
This commit is contained in:
Sergio R. Caprile
parent
95e3a8f3cc
commit
269600d875
@ -1,51 +1,29 @@
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CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
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CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
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CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
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CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_f4/Include
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CFLAGS += -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 $(CFLAGS_EXTRA)
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LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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SOURCES = main.c syscalls.c sysinit.c
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SOURCES += cmsis_f4/Source/Templates/gcc/startup_stm32f429xx.s # ST startup file. Compiler-dependent!
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# Mongoose options are defined in mongoose_config.h
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SOURCES += mongoose.c net.c packed_fs.c
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# Example specific build options. See README.md
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CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\"
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ifeq ($(OS),Windows_NT)
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RM = cmd /C del /Q /F /S
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else
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RM = rm -rf
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endif
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BOARD = f429
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IDE = GCC+make
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RTOS = baremetal
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WIZARD_URL ?= http://mongoose.ws/wizard
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all build example: firmware.bin
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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firmware.bin: wizard
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make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
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firmware.elf: cmsis_core cmsis_f4 $(SOURCES) hal.h link.ld
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
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wizard:
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hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
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&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
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unzip wizard.zip
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cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h
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flash: firmware.bin
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st-flash --reset write $< 0x8000000
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cmsis_core: # ARM CMSIS core headers
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git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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cmsis_f4: # ST CMSIS headers for STM32F4 series
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git clone --depth 1 -b v2.6.8 https://github.com/STMicroelectronics/cmsis_device_f4 $@
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# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
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DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/2
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update: firmware.bin
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
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test update: CFLAGS += -DUART_DEBUG=USART1
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test update: CFLAGS_EXTRA ="-DUART_DEBUG=USART1"
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test: update
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
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grep 'READY, IP:' /tmp/output.txt # Check for network init
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# grep 'MQTT connected' /tmp/output.txt # Check for MQTT connection success
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clean:
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$(RM) firmware.* *.su cmsis_core cmsis_f4
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rm -rf firmware.* wizard*
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@ -1,3 +1 @@
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# Baremetal web device dashboard on NUCLEO-F429ZI
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See https://mongoose.ws/tutorials/stm32/all-make-baremetal-builtin/
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See [Wizard](https://mongoose.ws/wizard/#/output?board=f429&ide=GCC+make&rtos=baremetal&file=README.md)
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@ -1,164 +0,0 @@
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// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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// https://www.st.com/resource/en/reference_manual/dm00031020-stm32f405-415-stm32f407-417-stm32f427-437-and-stm32f429-439-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
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// https://www.st.com/resource/en/datasheet/stm32f429zi.pdf
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#pragma once
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#include <stm32f429xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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#define LED1 PIN('B', 0) // On-board LED pin (green)
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#define LED2 PIN('B', 7) // On-board LED pin (blue)
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#define LED3 PIN('B', 14) // On-board LED pin (red)
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#define LED LED2 // Use blue LED for blinking
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// 6.3.3: APB1 clock <= 45MHz; APB2 clock <= 90MHz
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// 3.5.1, Table 11: configure flash latency (WS) in accordance to clock freq
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// 33.4: The AHB clock must be at least 25 MHz when Ethernet is used
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enum { APB1_PRE = 5 /* AHB clock / 4 */, APB2_PRE = 4 /* AHB clock / 2 */ };
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enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 180, PLL_P = 2 }; // Run at 180 Mhz
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#define FLASH_LATENCY 5
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#define SYS_FREQUENCY ((PLL_HSI * PLL_N / PLL_M / PLL_P) * 1000000)
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#define APB2_FREQUENCY (SYS_FREQUENCY / (BIT(APB2_PRE - 3)))
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#define APB1_FREQUENCY (SYS_FREQUENCY / (BIT(APB1_PRE - 3)))
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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#define GPIO(N) ((GPIO_TypeDef *) (0x40020000 + 0x400 * (N)))
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static GPIO_TypeDef *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
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static inline void gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int gpio_read(uint16_t pin) {
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return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->AHB1ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
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SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void irq_exti_attach(uint16_t pin) {
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uint8_t bank = (uint8_t) (PINBANK(pin)), n = (uint8_t) (PINNO(pin));
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SYSCFG->EXTICR[n / 4] &= ~(15UL << ((n % 4) * 4));
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SYSCFG->EXTICR[n / 4] |= (uint32_t) (bank << ((n % 4) * 4));
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EXTI->IMR |= BIT(n);
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EXTI->RTSR |= BIT(n);
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EXTI->FTSR |= BIT(n);
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int irqvec = n < 5 ? 6 + n : n < 10 ? 23 : 40; // IRQ vector index, 10.1.2
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NVIC_SetPriority(irqvec, 3);
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NVIC_EnableIRQ(irqvec);
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}
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#ifndef UART_DEBUG
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#define UART_DEBUG USART3
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#endif
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static inline void uart_init(USART_TypeDef *uart, unsigned long baud) {
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uint8_t af = 7; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
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if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
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if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(17);
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if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(18);
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if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
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if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
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if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
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gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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uart->CR1 = 0; // Disable this UART
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uart->BRR = freq / baud; // Set baud rate
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uart->CR1 |= BIT(13) | BIT(2) | BIT(3); // Set UE, RE, TE
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}
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static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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uart->DR = byte;
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while ((uart->SR & BIT(7)) == 0) spin(1);
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}
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static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(USART_TypeDef *uart) {
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return uart->SR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->DR & 255);
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}
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static inline void rng_init(void) {
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RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;
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RNG->CR |= RNG_CR_RNGEN;
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}
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static inline uint32_t rng_read(void) {
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while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
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return RNG->DR;
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}
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// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
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static inline void ethernet_init(void) {
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// Initialise Ethernet. Enable MAC GPIO pins, see
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// https://www.farnell.com/datasheets/2014265.pdf section 6.10
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uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),
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PIN('B', 13), PIN('C', 1), PIN('C', 4),
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PIN('C', 5), PIN('G', 11), PIN('G', 13)};
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for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
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gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
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GPIO_PULL_NONE, 11); // 11 is the Ethernet function
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}
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NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
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SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; // Use RMII. Goes first!
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RCC->AHB1ENR |=
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RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN;
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}
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#define UUID ((uint8_t *) UID_BASE) // Unique 96-bit chip ID. TRM 39.1
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// Helper macro for MAC generation
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ \
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2, UUID[0] ^ UUID[1], UUID[2] ^ UUID[3], UUID[4] ^ UUID[5], \
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UUID[6] ^ UUID[7] ^ UUID[8], UUID[9] ^ UUID[10] ^ UUID[11] \
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}
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@ -1,29 +0,0 @@
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ENTRY(Reset_Handler);
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MEMORY {
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flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
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sram(rwx) : ORIGIN = 0x20000000, LENGTH = 192k /* remaining 64k in a separate address space */
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}
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_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
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SECTIONS {
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.vectors : { KEEP(*(.isr_vector)) } > flash
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.text : { *(.text* .text.*) } > flash
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.rodata : { *(.rodata*) } > flash
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.data : {
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_sdata = .; /* for init_ram() */
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*(.first_data)
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*(.data SORT(.data.*))
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_edata = .; /* for init_ram() */
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} > sram AT > flash
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_sidata = LOADADDR(.data);
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.bss : {
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_sbss = .; /* for init_ram() */
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*(.bss SORT(.bss.*) COMMON)
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_ebss = .; /* for init_ram() */
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} > sram
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. = ALIGN(8);
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_end = .; /* for cmsis_gcc.h and init_ram() */
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}
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@ -1,72 +0,0 @@
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// Copyright (c) 2022-2023 Cesanta Software Limited
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// All rights reserved
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#include "hal.h"
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#include "mongoose.h"
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#include "net.h"
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#define BLINK_PERIOD_MS 1000 // LED blinking period in millis
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static volatile uint64_t s_ticks; // Milliseconds since boot
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void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
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s_ticks++;
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}
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uint64_t mg_millis(void) { // Let Mongoose use our uptime function
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return s_ticks; // Return number of milliseconds since boot
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}
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bool mg_random(void *buf, size_t len) { // Use on-board RNG
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for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
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uint32_t r = rng_read();
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memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
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}
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return true;
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}
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static void timer_fn(void *arg) {
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gpio_toggle(LED); // Blink LED
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struct mg_tcpip_if *ifp = arg; // And show
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const char *names[] = {"down", "up", "req", "ready"}; // network stats
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MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
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names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
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ifp->ndrop, ifp->nerr));
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}
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int main(void) {
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gpio_output(LED); // Setup blue LED
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uart_init(UART_DEBUG, 115200); // Initialise debug printf
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ethernet_init(); // Initialise ethernet pins
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MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000));
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struct mg_mgr mgr; // Initialise
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mg_mgr_init(&mgr); // Mongoose event manager
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mg_log_set(MG_LL_DEBUG); // Set log level
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// Initialise Mongoose network stack
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struct mg_tcpip_driver_stm32f_data driver_data = {.mdc_cr = 4};
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struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
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// Uncomment below for static configuration:
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// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
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// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
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// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
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.driver = &mg_tcpip_driver_stm32f,
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.driver_data = &driver_data};
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mg_tcpip_init(&mgr, &mif);
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mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
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MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
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while (mif.state != MG_TCPIP_STATE_READY) {
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mg_mgr_poll(&mgr, 0);
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}
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MG_INFO(("Initialising application..."));
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web_init(&mgr);
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MG_INFO(("Starting event loop"));
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for (;;) {
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mg_mgr_poll(&mgr, 0);
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}
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return 0;
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}
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@ -1 +0,0 @@
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../../../mongoose.c
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@ -1 +0,0 @@
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../../../mongoose.h
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@ -1,11 +0,0 @@
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#pragma once
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// See https://mongoose.ws/documentation/#build-options
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#define MG_ARCH MG_ARCH_NEWLIB
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#define MG_ENABLE_TCPIP 1
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#define MG_ENABLE_CUSTOM_MILLIS 1
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#define MG_ENABLE_CUSTOM_RANDOM 1
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#define MG_ENABLE_PACKED_FS 1
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#define MG_ENABLE_DRIVER_STM32F 1
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#define MG_ENABLE_LINES 1
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@ -1 +0,0 @@
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../../device-dashboard/net.c
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@ -1 +0,0 @@
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../../device-dashboard/net.h
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@ -1 +0,0 @@
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../../device-dashboard/packed_fs.c
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@ -1,88 +0,0 @@
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#include <sys/stat.h>
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#include "hal.h"
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int _fstat(int fd, struct stat *st) {
|
||||
if (fd < 0) return -1;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
extern char _end;
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
unsigned char x = 0, *heap_end = (unsigned char *)((size_t) &x - 512);
|
||||
(void) x;
|
||||
if (heap == NULL) heap = (unsigned char *) &_end;
|
||||
prev_heap = heap;
|
||||
if (heap + incr > heap_end) return (void *) -1;
|
||||
heap += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int mkdir(const char *path, mode_t mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {}
|
||||
@ -1,29 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// This file contains essentials required by the CMSIS:
|
||||
// uint32_t SystemCoreClock - holds the system core clock value
|
||||
// SystemInit() - initialises the system, e.g. sets up clocks
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
asm("DSB");
|
||||
asm("ISB");
|
||||
FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch
|
||||
RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers
|
||||
RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P
|
||||
RCC->PLLCFGR |= PLL_M | (PLL_N << 6); // Set PLL_M and PLL_N
|
||||
RCC->CR |= BIT(24); // Enable PLL
|
||||
while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR = (APB1_PRE << 10) | (APB2_PRE << 13); // Set prescalers
|
||||
RCC->CFGR |= 2; // Set clock source to PLL
|
||||
while ((RCC->CFGR & 12) == 0) spin(1); // Wait until done
|
||||
|
||||
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; // Enable SYSCFG
|
||||
rng_init(); // Initialise random number generator
|
||||
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user