Merge pull request #2770 from cesanta/1170fr

Add FreeRTOS example

.github/workflows/nightly.yml

@@ -376,6 +376,7 @@ jobs:
           - path: nxp/rt1060-evk-make-baremetal-builtin
           - path: nxp/rt1060-evk-make-freertos-builtin
           - path: nxp/rt1170-evk-make-baremetal-builtin
+          - path: nxp/rt1170-evk-make-freertos-builtin
           - path: renesas/ek-ra6m4-make-baremetal-builtin
           - path: rp2040/pico-rndis-dashboard
           - path: rp2040/pico-w
@@ -579,7 +580,7 @@ jobs:
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
     - run: make -C examples/nxp/rt1170-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-#    - run: make -C examples/nxp/rt1170-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C examples/nxp/rt1170-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 
   test_ra6m4:
     runs-on: ubuntu-latest

.github/workflows/quicktest.yml

@@ -248,6 +248,7 @@ jobs:
           - path: nxp/rt1060-evk-make-baremetal-builtin
           - path: nxp/rt1060-evk-make-freertos-builtin
           - path: nxp/rt1170-evk-make-baremetal-builtin
+          - path: nxp/rt1170-evk-make-freertos-builtin
           - path: renesas/ek-ra6m4-make-baremetal-builtin
           - path: rp2040/pico-rndis-dashboard
           - path: rp2040/pico-w
@@ -658,11 +659,11 @@ jobs:
         if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/nxp/rt1170-evk-make-baremetal-builtin'; then
           make -C examples/nxp/rt1170-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
         fi
-#    - if: ${{ env.GO == 1 }}
+    - if: ${{ env.GO == 1 }}
-#      run: |
+      run: |
-#        if ./test/match_changed_files.sh 'examples/nxp/rt1170-evk-make-freertos-builtin'; then
+        if ./test/match_changed_files.sh 'examples/nxp/rt1170-evk-make-freertos-builtin'; then
-#          make -C examples/nxp/rt1170-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+          make -C examples/nxp/rt1170-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-#        fi
+        fi
 
   test_ra6m4:
     runs-on: ubuntu-latest

examples/nxp/rt1170-evk-make-freertos-builtin/FreeRTOSConfig.h

@@ -0,0 +1,38 @@
+#pragma once
+
+#include "hal.h"
+
+#define configUSE_PREEMPTION 1
+#define configCPU_CLOCK_HZ SYS_FREQUENCY
+#define configTICK_RATE_HZ 1000
+#define configMAX_PRIORITIES 5
+#define configUSE_16_BIT_TICKS 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TIMERS 0
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configMINIMAL_STACK_SIZE 128
+#define configTOTAL_HEAP_SIZE (1024 * 32)
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1  // trying
+
+#ifdef __NVIC_PRIO_BITS
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4
+#endif
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+#define configKERNEL_INTERRUPT_PRIORITY \
+  (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
+  (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+#define configASSERT(expr) \
+  if (!(expr)) printf("FAILURE %s:%d: %s\n", __FILE__, __LINE__, #expr)
+
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+//#define xPortSysTickHandler SysTick_Handler

examples/nxp/rt1170-evk-make-freertos-builtin/Makefile

@@ -0,0 +1,86 @@
+CFLAGS  = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
+CFLAGS += -Wformat-truncation -fno-common -Wconversion
+CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
+CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MIMXRT1176
+CFLAGS += -Icmsis_mcu/devices/MIMXRT1176/drivers -DCPU_MIMXRT1176DVMAA_cm7
+CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
+CFLAGS += -Wno-conversion -Wno-unused-parameter # due to NXP FSL code
+LDSCRIPT = link.ld
+LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map 
+
+SOURCES = main.c syscalls.c sysinit.c
+SOURCES += cmsis_mcu/devices/MIMXRT1176/gcc/startup_MIMXRT1176_cm7.S # NXP startup file. Compiler-dependent!
+SOURCES += cmsis_mcu/devices/MIMXRT1176/drivers/fsl_clock.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_anatop_ai.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_pmu.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_dcdc.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_common_arm.c # NXP support files
+CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS	# Make startup code work as expected
+
+# FreeRTOS. RT1170 has a Cortex-M7 r1p2 core, FreeRTOS recommends using CM4F port for non-r0p1 CM7 micros
+SOURCES += FreeRTOS-Kernel/portable/MemMang/heap_4.c
+SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c
+CFLAGS += -IFreeRTOS-Kernel/include 
+CFLAGS += -IFreeRTOS-Kernel/portable/GCC/ARM_CM4F -Wno-conversion
+
+# Mongoose options are defined in mongoose_config.h
+SOURCES += mongoose.c net.c packed_fs.c
+
+# Example specific build options. See README.md
+CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\"
+
+ifeq ($(OS),Windows_NT)
+  RM = cmd /C del /Q /F /S
+else
+  RM = rm -rf
+endif
+
+all build example update: SOURCES += flash_image.c
+all build example: firmware.bin
+
+ram: LDSCRIPT = link_ram.ld
+ram: firmware.bin
+
+firmware.bin: firmware.elf
+	arm-none-eabi-objcopy -O binary $< $@
+
+firmware.elf: FreeRTOS-Kernel cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld link.ld Makefile mongoose_config.h
+	arm-none-eabi-gcc $(SOURCES) $(wildcard FreeRTOS-Kernel/*.c) $(CFLAGS) $(LDFLAGS) -o $@
+	arm-none-eabi-size $@
+
+flash: firmware.bin
+# flash
+
+cmsis_core:     # ARM CMSIS core headers
+	git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
+cmsis_mcu:
+	curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1176_DFP.18.0.0.pack -o $@.zip
+	mkdir $@ && cd $@ && unzip -q ../$@.zip
+FreeRTOS-Kernel:  # FreeRTOS sources
+	git clone --depth 1 -b V10.5.0 https://github.com/FreeRTOS/FreeRTOS-Kernel $@
+
+# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
+DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/15
+update: firmware.bin
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
+
+update updateram: CFLAGS += -DUART_DEBUG=LPUART2
+
+test: update
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
+	grep 'READY, IP:' /tmp/output.txt       # Check for network init
+
+
+updateram: ram
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @firmware.bin
+	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
+	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1"}'
+	PC=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,4"}' | jq -r .resp[5:]` && \
+	SP=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,0"}' | jq -r .resp[5:]` && \
+	REQ="wm,e000ed08,0 wr,d,$$SP wr,f,$$PC" && \
+	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"'"$$REQ"'"}'
+	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0001"}'
+
+testram: updateram
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
+	grep 'READY, IP:' /tmp/output.txt       # Check for network init
+
+
+clean:
+	$(RM) firmware.* *.su cmsis_core cmsis_mcu FreeRTOS-Kernel *.zip

examples/nxp/rt1170-evk-make-freertos-builtin/dcd.h

@@ -0,0 +1 @@
+../rt1170-evk-make-baremetal-builtin/dcd.h

examples/nxp/rt1170-evk-make-freertos-builtin/flash_image.c

@@ -0,0 +1 @@
+../rt1170-evk-make-baremetal-builtin/flash_image.c

examples/nxp/rt1170-evk-make-freertos-builtin/hal.h

@@ -0,0 +1,337 @@
+// Copyright (c) 2024 Cesanta Software Limited
+// All rights reserved
+// https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM
+// https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKBHUG
+
+#pragma once
+
+#include "MIMXRT1176_cm7.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#define BIT(x) (1UL << (x))
+#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
+#define PIN(bank, num) ((((bank) - '0') << 8) | (num))
+#define PINNO(pin) (pin & 255)
+#define PINBANK(pin) (pin >> 8)
+
+// Use LED for blinking, D6: GPIO_AD_04. GPIO3.3 (schematics, RM)
+#define LED PIN('3', 3)
+
+#ifndef UART_DEBUG
+#define UART_DEBUG LPUART1
+#endif
+
+// No settable constants, see sysinit.c
+#define SYS_FREQUENCY 996000000UL
+
+static inline void spin(volatile uint32_t count) {
+  while (count--) (void) 0;
+}
+
+// Use "Unassigned/Domain Mode"
+static inline void clock_periph(uint32_t index, bool val) {
+  CCM->LPCG[index].DIRECT = val ? 1 : 0;  // (15.9.1.25)
+}
+
+// which peripheral feeds the pin
+static inline void gpio_mux_config(uint16_t index, uint8_t af) {
+  IOMUXC->SW_MUX_CTL_PAD[index] = af;
+}
+
+// which pin feeds the peripheral (2nd stage)
+static inline void periph_mux_config(uint16_t index, uint8_t in) {
+  IOMUXC->SELECT_INPUT[index] = in;
+}
+
+// CM7_GPIOx not supported
+enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
+enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
+enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH };
+enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
+static inline GPIO_Type *gpio_bank(uint16_t pin) {
+  static const GPIO_Type *g[] = {NULL,   GPIO1,  GPIO2,  GPIO3, GPIO4,
+                                 GPIO5,  GPIO6,  GPIO7,  GPIO8, GPIO9,
+                                 GPIO10, GPIO11, GPIO12, GPIO13};
+  return (GPIO_Type *) g[PINBANK(pin)];
+}
+
+// pin driver/pull-up/down configuration (allow both cores)
+static inline void gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed,
+                                   uint8_t pull) {
+  if (index < kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 ||
+      (index >= kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 &&
+       index < kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00)) {
+    IOMUXC->SW_PAD_CTL_PAD[index] =
+        IOMUXC_SW_PAD_CTL_PAD_PDRV(speed == GPIO_SPEED_LOW) |
+        IOMUXC_SW_PAD_CTL_PAD_ODE(type) | IOMUXC_SW_PAD_CTL_PAD_PULL(pull);
+  } else {
+    bool dopull = pull > 0;
+    if (dopull) pull = (pull == GPIO_PULL_UP);
+    IOMUXC->SW_PAD_CTL_PAD[index] =
+        IOMUXC_SW_PAD_CTL_PAD_DSE(speed != GPIO_SPEED_LOW) |
+        IOMUXC_SW_PAD_CTL_PAD_ODE(type) | IOMUXC_SW_PAD_CTL_PAD_PUE(dopull) |
+        IOMUXC_SW_PAD_CTL_PAD_PUS(pull) |
+        IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH);
+  }
+}
+
+static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
+                             uint8_t speed, uint8_t pull) {
+  GPIO_Type *gpio = gpio_bank(pin);
+  uint8_t bit = (uint8_t) PINNO(pin);
+  uint32_t mask = (uint32_t) BIT(PINNO(pin));
+
+  clock_periph(51, 1);     // clk_enable_gpio (15.5.4 Table 15-5)
+  clock_periph(49, 1);     // clk_enable_iomuxc (15.5.4 Table 15-5)
+  switch (PINBANK(pin)) {  // (11.1.1 Table 11-1)
+    case 1:
+      gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 + bit, 5);
+      gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 + bit, type, speed,
+                      pull);
+      break;
+    case 2:
+      IOMUXC_GPR->GPR40 = 0;  // select GPIO2
+      IOMUXC_GPR->GPR41 = 0;  // select GPIO2
+      gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 + bit, 5);
+      gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 + bit, type, speed,
+                      pull);
+      break;
+    case 3:
+      IOMUXC_GPR->GPR42 = 0;  // select GPIO3
+      IOMUXC_GPR->GPR43 = 0;  // select GPIO3
+      gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 + bit, 5);
+      gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 + bit, type, speed,
+                      pull);
+      break;
+    case 4:
+      gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 + bit, 5);
+      gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 + bit, type, speed,
+                      pull);
+      break;
+    default:
+      // TODO(): support GPIO5-13, 10-15 requires redefinition of PIN() macro
+      break;
+  }
+
+  gpio->IMR &= ~mask;
+  if (mode == GPIO_MODE_INPUT) {
+    gpio->GDIR &= ~mask;
+  } else {
+    gpio->GDIR |= mask;
+  }
+}
+static inline void gpio_input(uint16_t pin) {
+  gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
+            GPIO_PULL_NONE);
+}
+static inline void gpio_output(uint16_t pin) {
+  gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
+            GPIO_PULL_NONE);
+}
+
+static inline bool gpio_read(uint16_t pin) {
+  GPIO_Type *gpio = gpio_bank(pin);
+  uint32_t mask = (uint32_t) BIT(PINNO(pin));
+  return gpio->DR & mask;
+}
+static inline void gpio_write(uint16_t pin, bool value) {
+  GPIO_Type *gpio = gpio_bank(pin);
+  uint32_t mask = (uint32_t) BIT(PINNO(pin));
+  if (value) {
+    gpio->DR |= mask;
+  } else {
+    gpio->DR &= ~mask;
+  }
+}
+static inline void gpio_toggle(uint16_t pin) {
+  gpio_write(pin, !gpio_read(pin));
+}
+
+// 15.3 Table 15-2: uart_clk_root
+// 15.4: lpuart*_clk_root 15.5.3 Table 15-4; 15.9.1.2; select OSC_24M
+static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
+  uint8_t af = 0;                           // Alternate function
+  uint16_t mr = 0, pr = 0, mt = 0, pt = 0;  // pins
+  uint32_t freq = 24000000;                 // uart_clk_root frequency
+  if (uart == LPUART1) {
+    af = 0;
+    mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24;
+    pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24;
+    mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25;
+    pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25;
+    // configure clock root source and divisor /1, enable peripheral clock
+    CCM->CLOCK_ROOT[25].CONTROL =
+        CCM_CLOCK_ROOT_CONTROL_MUX(1) | CCM_CLOCK_ROOT_CONTROL_DIV(0);
+    clock_periph(86, 1);  // (15.5.4 Table 15-5)
+    periph_mux_config(kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT, 0);
+    periph_mux_config(kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT, 0);
+  } else if (uart == LPUART2) {
+    af = 2;
+    mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10;
+    pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10;
+    mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11;
+    pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11;
+    CCM->CLOCK_ROOT[26].CONTROL =
+        CCM_CLOCK_ROOT_CONTROL_MUX(1) | CCM_CLOCK_ROOT_CONTROL_DIV(0);
+    clock_periph(87, 1);  // (15.5.4 Table 15-5)
+  }
+  clock_periph(49, 1);  // clk_enable_iomuxc (15.5.4 Table 15-5)
+  gpio_mux_config(mt, af);
+  gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_NONE);
+  gpio_mux_config(mr, af);
+  gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
+
+  uart->GLOBAL |= LPUART_GLOBAL_RST_MASK;  // reset, CTRL = 0, defaults
+  uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
+  uart->BAUD = LPUART_BAUD_OSR(16 - 1) |
+               LPUART_BAUD_SBR(freq / (16 * baud));  // Rx sample at 16x
+  uart->CTRL = LPUART_CTRL_IDLECFG(1) |
+               LPUART_CTRL_ILT(1);  // no parity, idle 2 chars after 1 stop bit
+  uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
+}
+
+static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
+  uart->DATA = byte;
+  while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
+}
+static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
+  while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
+}
+static inline int uart_read_ready(LPUART_Type *uart) {
+  (void) uart;
+  return uart->STAT & LPUART_STAT_RDRF_MASK;
+}
+static inline uint8_t uart_read_byte(LPUART_Type *uart) {
+  return (uint8_t) (uart->DATA & 255);
+}
+
+
+static inline void lpsr_mux_config(uint16_t index, uint8_t af) {
+  IOMUXC_LPSR->SW_MUX_CTL_PAD[index] = af;
+}
+
+static inline void lpsr_pad_config(uint16_t index, uint8_t type, uint8_t speed,
+                                   uint8_t pull) {
+  bool dopull = pull > 0;
+  if (dopull) pull = (pull == GPIO_PULL_UP);
+  IOMUXC_LPSR->SW_PAD_CTL_PAD[index] =
+      IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(speed != GPIO_SPEED_LOW) |
+      IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(type) |
+      IOMUXC_SW_PAD_CTL_PAD_PUE(dopull) | IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(pull) |
+      IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH);
+}
+
+#include "fsl_clock.h"
+
+// - 15.4 clock tree
+// - 15.3 Table 15-2: ENET1_CLK_ROOT <= 50MHz
+// - PHY has no xtal, XI driven from ENET_REF_CLK (labeled as ENET_TX_REF_CLK
+// (GPIO_DISP_B2_05)), generated by the MCU
+// - PHY RST connected to GPIO12.12 (GPIO_LPSR_12);
+// - 60.4 REF_CLK is RMII mode reference clock for Rx, Tx, and SMI; it is I/O
+static inline void ethernet_init(void) {
+  const clock_sys_pll1_config_t pll1 = {.pllDiv2En = true};
+  CLOCK_InitSysPll1(&pll1);  // setup PLL1 and clock ENET from it
+  // configure clock root source PLL1/2 and divisor /10, enable peripheral clock
+  CCM->CLOCK_ROOT[51].CONTROL =
+      CCM_CLOCK_ROOT_CONTROL_MUX(4) | CCM_CLOCK_ROOT_CONTROL_DIV(10 - 1);
+  clock_periph(112, 1);  // clk_enable_enet (15.5.4 Table 15-5)
+
+  clock_periph(51, 1);  // clk_enable_gpio (15.5.4 Table 15-5)
+  clock_periph(50, 1);  // clk_enable_iomuxc_lpsr (15.5.4 Table 15-5)
+  clock_periph(49, 1);  // clk_enable_iomuxc (15.5.4 Table 15-5)
+  lpsr_mux_config(kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12,
+                  10);  // set GPIO12.12 as GPIO (PHY \RST)
+  lpsr_pad_config(kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12,
+                  GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
+  GPIO12->IMR &= ~BIT(12);
+  GPIO12->GDIR |= BIT(12);
+  GPIO12->DR &= ~BIT(12);  // reset PHY
+
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05,
+                  2);  // set for ENET_REF_CLK
+  IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05] |=
+      IOMUXC_SW_MUX_CTL_PAD_SION(1);  // loop signal back from pin
+  periph_mux_config(kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT,
+                    1);  // drive peripheral from DISP_B2_05, so RMII clock is
+                         // taken from ENET_REF_CLK
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05, GPIO_OTYPE_PUSH_PULL,
+                  GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+  IOMUXC_GPR->GPR4 |=
+      IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(1);  // Set ENET_REF_CLK as output
+
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06,
+                  1);  // set for RXDATA0
+  periph_mux_config(kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0,
+                    1);  // drive peripheral from DISP_B2_06
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06, GPIO_OTYPE_PUSH_PULL,
+                  GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
+
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07,
+                  1);  // set for RXDATA1
+  periph_mux_config(kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1,
+                    1);  // drive peripheral from DISP_B2_07
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07, GPIO_OTYPE_PUSH_PULL,
+                  GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
+
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08, 1);  // set for CRS
+  periph_mux_config(kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT,
+                    1);  // drive peripheral from DISP_B2_08
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08, GPIO_OTYPE_PUSH_PULL,
+                  GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
+
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09, 1);  // set for RXERR
+  periph_mux_config(kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT,
+                    1);  // drive peripheral from DISP_B2_09
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09, GPIO_OTYPE_PUSH_PULL,
+                  GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
+
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02,
+                  1);  // set for TXDATA0
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02, GPIO_OTYPE_PUSH_PULL,
+                  GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03,
+                  1);  // set for TXDATA1
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03, GPIO_OTYPE_PUSH_PULL,
+                  GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04, 1);  // set for TXEN
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04, GPIO_OTYPE_PUSH_PULL,
+                  GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32, 3);  // set for MDC
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32, GPIO_OTYPE_PUSH_PULL,
+                  GPIO_SPEED_MEDIUM, GPIO_PULL_NONE);
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33, 3);  // set for MDIO
+  periph_mux_config(kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT,
+                    1);  // drive peripheral from AD_33
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33, GPIO_OTYPE_PUSH_PULL,
+                  GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
+
+  IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_ENET_MASK;  // ERR050396
+  gpio_init(PIN('3', 11), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM,
+            GPIO_PULL_UP);  // setup IRQ (pulled-up)(not used)
+  spin(10000);              // keep PHY RST low for a while
+  GPIO12->DR |= BIT(12);    // deassert RST
+
+  clock_periph(112, 1);       // clk_enable_enet (15.5.4 Table 15-5)
+  NVIC_EnableIRQ(ENET_IRQn);  // Setup Ethernet IRQ handler
+}
+
+// Helper macro for MAC generation, byte reads not allowed
+#define GENERATE_LOCALLY_ADMINISTERED_MAC()                                    \
+  {                                                                            \
+    2, OCOTP->FUSEN[16].FUSE & 255, (OCOTP->FUSEN[16].FUSE >> 10) & 255,       \
+        ((OCOTP->FUSEN[16].FUSE >> 19) ^ (OCOTP->FUSEN[17].FUSE >> 19)) & 255, \
+        (OCOTP->FUSEN[17].FUSE >> 10) & 255, OCOTP->FUSEN[17].FUSE & 255       \
+  }
+
+static inline void flash_init(void) {  // QSPI in FlexSPI
+  // set pins
+  clock_periph(49, 1);  // clk_enable_iomuxc (15.5.4 Table 15-5)
+#if 0
+#endif
+}

examples/nxp/rt1170-evk-make-freertos-builtin/link.ld

@@ -0,0 +1,24 @@
+ENTRY(Reset_Handler);
+MEMORY {
+  flash_hdr(rx)  : ORIGIN = 0x30000000, LENGTH = 8k
+  flash_irq(rx)  : ORIGIN = 0x30002000, LENGTH = 1k
+  flash_code(rx) : ORIGIN = 0x30002400, LENGTH = 65527k
+
+  itcram(rx)       : ORIGIN = 0x00000000, LENGTH = 256k
+  dtcram(rw)       : ORIGIN = 0x20000000, LENGTH = 256k
+  ocram(rw)        : ORIGIN = 0x20240000, LENGTH = 512k   /* Is this cached ? */
+}
+__StackTop = ORIGIN(dtcram) + LENGTH(dtcram);
+
+/* TODO(): separate itcram and go back to using dtcram for data and bss when ota is finished */
+
+SECTIONS {
+  .hdr  : { FILL(0xff) ; . = 0x400 ; KEEP(*(.cfg)) . = 0x1000 ; KEEP(*(.ivt)) . = 0x1020 ;
+            KEEP(*(.dat)) . = 0x1030 ; KEEP(*(.dcd)) . = 0x2000 ;} >flash_hdr
+  .irq  : { KEEP(*(.isr_vector)) }  > flash_irq
+  .text : { *(.text* .text.*) *(.rodata*) ; } > flash_code
+  .data : { __data_start__ = .; *(.data SORT(.data.*)) *(.iram) __data_end__ = .; } > itcram AT > flash_code
+  __etext = LOADADDR(.data);
+  .bss  : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > itcram
+  _end = .;
+}

examples/nxp/rt1170-evk-make-freertos-builtin/link_ram.ld

@@ -0,0 +1,16 @@
+ENTRY(Reset_Handler);
+MEMORY {
+  itcram(rx)       : ORIGIN = 0x00000000, LENGTH = 256k
+  dtcram(rw)       : ORIGIN = 0x20000000, LENGTH = 256k
+  ocram(rw)        : ORIGIN = 0x20240000, LENGTH = 512k   /* Is this cached ? */
+}
+__StackTop = ORIGIN(dtcram) + LENGTH(dtcram);
+
+SECTIONS {
+  .irq  : { KEEP(*(.isr_vector)) }  > itcram
+  .text : { *(.text* .text.*) *(.rodata*) ; } > itcram
+  .data : { __data_start__ = .; *(.data SORT(.data.*)) __data_end__ = .; } > dtcram AT > itcram
+  __etext = LOADADDR(.data);
+  .bss  : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > dtcram
+  _end = .;
+}

examples/nxp/rt1170-evk-make-freertos-builtin/main.c

@@ -0,0 +1,76 @@
+// Copyright (c) 2024 Cesanta Software Limited
+// All rights reserved
+
+#include "hal.h"
+#include "mongoose.h"
+#include "net.h"
+
+#define BLINK_PERIOD_MS 1000  // LED blinking period in millis
+
+// workaround optimizer somehow causing SysTick to fire before FreeRTOS has
+// fully initialized
+extern void xPortSysTickHandler(void);
+void SysTick_Handler(void) {
+  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
+    xPortSysTickHandler();
+}
+
+static void timer_fn(void *arg) {
+  struct mg_tcpip_if *ifp = arg;                         // And show
+  const char *names[] = {"down", "up", "req", "ready"};  // network stats
+  MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
+           names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
+           ifp->ndrop, ifp->nerr));
+}
+
+static void server(void *args) {
+  struct mg_mgr mgr;        // Initialise Mongoose event manager
+  mg_mgr_init(&mgr);        // and attach it to the interface
+  mg_log_set(MG_LL_DEBUG);  // Set log level
+
+  // Initialise Mongoose network stack
+  ethernet_init();          // Initialise ethernet pins
+  struct mg_tcpip_driver_imxrt_data driver_data = {.mdc_cr = 24, .phy_addr = 3};
+  struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
+                            // Uncomment below for static configuration:
+                            // .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
+                            // .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
+                            // .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
+                            .driver = &mg_tcpip_driver_imxrt,
+                            .driver_data = &driver_data};
+  mg_tcpip_init(&mgr, &mif);
+  mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
+
+  MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
+  while (mif.state != MG_TCPIP_STATE_READY) {
+    mg_mgr_poll(&mgr, 0);
+  }
+
+  MG_INFO(("Initialising application..."));
+  web_init(&mgr);
+
+  MG_INFO(("Starting event loop"));
+  for (;;) mg_mgr_poll(&mgr, 1);  // Infinite event loop
+  (void) args;
+}
+
+static void blinker(void *args) {
+  gpio_output(LED);  // Setup blue LED
+  for (;;) {
+    gpio_toggle(LED);
+    vTaskDelay(pdMS_TO_TICKS(BLINK_PERIOD_MS));
+  }
+  (void) args;
+}
+
+int main(void) {
+  uart_init(UART_DEBUG, 115200);  // Initialise UART
+
+  // Start tasks. NOTE: stack sizes are in 32-bit words
+  xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL);
+
+  vTaskStartScheduler();  // This blocks
+  return 0;
+}
+

examples/nxp/rt1170-evk-make-freertos-builtin/mongoose.c

@@ -0,0 +1 @@
+../../../mongoose.c

examples/nxp/rt1170-evk-make-freertos-builtin/mongoose.h

@@ -0,0 +1 @@
+../../../mongoose.h

examples/nxp/rt1170-evk-make-freertos-builtin/mongoose_config.h

@@ -0,0 +1,14 @@
+#pragma once
+
+#include <errno.h>	// we are not using lwIP
+
+// See https://mongoose.ws/documentation/#build-options
+#define MG_ARCH MG_ARCH_FREERTOS
+
+#define MG_ENABLE_TCPIP 1
+#define MG_ENABLE_DRIVER_IMXRT 1
+#define MG_DRIVER_IMXRT_RT11 1
+#define MG_ENABLE_TCPIP_DRIVER_INIT 0
+#define MG_IO_SIZE 256
+#define MG_ENABLE_PACKED_FS 1
+#define MG_ENABLE_TCPIP_PRINT_DEBUG_STATS 1

examples/nxp/rt1170-evk-make-freertos-builtin/net.c

@@ -0,0 +1 @@
+../../device-dashboard/net.c

examples/nxp/rt1170-evk-make-freertos-builtin/net.h

@@ -0,0 +1 @@
+../../device-dashboard/net.h

examples/nxp/rt1170-evk-make-freertos-builtin/packed_fs.c

@@ -0,0 +1 @@
+../../device-dashboard/packed_fs.c

examples/nxp/rt1170-evk-make-freertos-builtin/syscalls.c

@@ -0,0 +1,85 @@
+#include <sys/stat.h>
+
+#include "hal.h"
+
+int _fstat(int fd, struct stat *st) {
+  if (fd < 0) return -1;
+  st->st_mode = S_IFCHR;
+  return 0;
+}
+
+void *_sbrk(int incr) {
+  extern char _end;
+  static unsigned char *heap = NULL;
+  unsigned char *prev_heap;
+  if (heap == NULL) heap = (unsigned char *) &_end;
+  prev_heap = heap;
+  heap += incr;
+  return prev_heap;
+}
+
+int _open(const char *path) {
+  (void) path;
+  return -1;
+}
+
+int _close(int fd) {
+  (void) fd;
+  return -1;
+}
+
+int _isatty(int fd) {
+  (void) fd;
+  return 1;
+}
+
+int _lseek(int fd, int ptr, int dir) {
+  (void) fd, (void) ptr, (void) dir;
+  return 0;
+}
+
+void _exit(int status) {
+  (void) status;
+  for (;;) asm volatile("BKPT #0");
+}
+
+void _kill(int pid, int sig) {
+  (void) pid, (void) sig;
+}
+
+int _getpid(void) {
+  return -1;
+}
+
+int _write(int fd, char *ptr, int len) {
+  (void) fd, (void) ptr, (void) len;
+  if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
+  return -1;
+}
+
+int _read(int fd, char *ptr, int len) {
+  (void) fd, (void) ptr, (void) len;
+  return -1;
+}
+
+int _link(const char *a, const char *b) {
+  (void) a, (void) b;
+  return -1;
+}
+
+int _unlink(const char *a) {
+  (void) a;
+  return -1;
+}
+
+int _stat(const char *path, struct stat *st) {
+  (void) path, (void) st;
+  return -1;
+}
+
+int mkdir(const char *path, mode_t mode) {
+  (void) path, (void) mode;
+  return -1;
+}
+
+void _init(void) {}

examples/nxp/rt1170-evk-make-freertos-builtin/sysinit.c

@@ -0,0 +1,48 @@
+// Copyright (c) 2024 Cesanta Software Limited
+// All rights reserved
+//
+// This file contains essentials required by the CMSIS:
+// uint32_t SystemCoreClock - holds the system core clock value
+// SystemInit() - initialises the system, e.g. sets up clocks
+
+#include "hal.h"
+#include "fsl_clock.h"
+#include "fsl_dcdc.h"
+#include "fsl_pmu.h"
+
+uint32_t SystemCoreClock = SYS_FREQUENCY;
+
+// - 15.4 clock tree
+// 15.4: M7_CLK_ROOT
+// 15.5.3 Table 15-4; 15.9.1.2; select PLL_ARM_CLK
+// 15.8.2 PLL Enable Sequence
+// - Datasheet 4.1.3, Table 11: "Overdrive" run mode particulars
+void SystemInit(void) {  // Called automatically by startup code (ints masked)
+  SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));  // Enable FPU
+  asm("DSB");
+  asm("ISB");
+  // 79.5.2: Disable watchdogS after reset (unlocked)
+  RTWDOG3->CS &= ~RTWDOG_CS_EN_MASK;
+  RTWDOG3->TOVAL = 0xFFFF;
+  while (RTWDOG3->CS & RTWDOG_CS_ULK_MASK) spin(1);  // wait for lock
+  while ((RTWDOG3->CS & RTWDOG_CS_RCS_MASK) == 0)
+    spin(1);  // wait for new config
+  RTWDOG4->CS &= ~RTWDOG_CS_EN_MASK;
+  RTWDOG4->TOVAL = 0xFFFF;
+  while (RTWDOG4->CS & RTWDOG_CS_ULK_MASK) spin(1);  // wait for lock
+  while ((RTWDOG4->CS & RTWDOG_CS_RCS_MASK) == 0)
+    spin(1);  // wait for new config
+  ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1);
+  while ((ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK) == 0)
+    spin(1);  // wait until it is stable
+  DCDC_BootIntoDCM(DCDC);  // Enable "overdrive" mode as needed
+  DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
+  PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, (OCOTP->FUSEN[7].FUSE & BIT(4)) == 0);
+  const clock_arm_pll_config_t armpll =  {.loopDivider = 166, .postDivider = 0};
+  CLOCK_InitArmPll(&armpll);  // Set clock to 996MHz
+  CCM->CLOCK_ROOT[0].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(4); // /1
+
+  // rng_init();  // TRNG is part or CAAM and there is no info on that
+  // NXP startup code calls SystemInit BEFORE initializing RAM...
+  SysTick_Config(SYS_FREQUENCY / 1000);  // Sys tick every 1ms
+}