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Add MG_PHY_DISABLE_AUTONEG option

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This commit is contained in:
Sergey Lyubka 2024-11-14 14:08:15 +00:00
parent 85414cfec2
commit 41a567f089
4 changed files with 42 additions and 50 deletions
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35
mongoose.c
View File

@ -17628,8 +17628,8 @@ struct mg_tcpip_driver mg_tcpip_driver_imxrt = {mg_tcpip_driver_imxrt_init,
#endif
enum { // ID1 ID2
MG_PHY_KSZ8x = 0x22, // 0022 1561 - KSZ8081RNB
enum { // ID1 ID2
MG_PHY_KSZ8x = 0x22, // 0022 1561 - KSZ8081RNB
MG_PHY_DP83x = 0x2000,
MG_PHY_DP83867 = 0xa231, // 2000 a231 - TI DP83867I
MG_PHY_DP83825 = 0xa140, // 2000 a140 - TI DP83825I
@ -17658,23 +17658,15 @@ static const char *mg_phy_id_to_str(uint16_t id1, uint16_t id2) {
switch (id1) {
case MG_PHY_DP83x:
switch (id2) {
case MG_PHY_DP83867:
return "DP83867";
case MG_PHY_DP83848:
return "DP83848";
case MG_PHY_DP83825:
return "DP83825";
default:
return "DP83x";
case MG_PHY_DP83867: return "DP83867";
case MG_PHY_DP83848: return "DP83848";
case MG_PHY_DP83825: return "DP83825";
default: return "DP83x";
}
case MG_PHY_KSZ8x:
return "KSZ8x";
case MG_PHY_LAN87x:
return "LAN87x";
case MG_PHY_RTL8201:
return "RTL8201";
default:
return "unknown";
case MG_PHY_KSZ8x: return "KSZ8x";
case MG_PHY_LAN87x: return "LAN87x";
case MG_PHY_RTL8201: return "RTL8201";
default: return "unknown";
}
(void) id2;
}
@ -17689,6 +17681,13 @@ void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) {
id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2);
MG_INFO(("PHY ID: %#04x %#04x (%s)", id1, id2, mg_phy_id_to_str(id1, id2)));
if (config & MG_PHY_DISABLE_AUTONEG) {
uint16_t val = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
phy->write_reg(phy_addr, MG_PHY_REG_BCR, val & (uint16_t) ~MG_BIT(12));
val = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
phy->write_reg(phy_addr, MG_PHY_REG_BCR, (uint16_t) MG_BIT(9));
}
if (id1 == MG_PHY_DP83x && id2 == MG_PHY_DP83867) {
phy->write_reg(phy_addr, 0x0d, 0x1f); // write 0x10d to IO_MUX_CFG (0x0170)
phy->write_reg(phy_addr, 0x0e, 0x170);

11
mongoose.h
View File

@ -2928,13 +2928,10 @@ struct mg_phy {
void (*write_reg)(uint8_t addr, uint8_t reg, uint16_t value);
};
// PHY configuration settings, bitmask
enum {
// Set if PHY LEDs are connected to ground
MG_PHY_LEDS_ACTIVE_HIGH = (1 << 0),
// Set when PHY clocks MAC. Otherwise, MAC clocks PHY
MG_PHY_CLOCKS_MAC = (1 << 1),
};
// MG_TCPIP_PHY_CONF configuration settings, bitmask of the following:
#define MG_PHY_LEDS_ACTIVE_HIGH 1 // PHY LEDs are connected to ground
#define MG_PHY_CLOCKS_MAC 2 // PHY clocks MAC. Otherwise, MAC clocks PHY
#define MG_PHY_DISABLE_AUTONEG 4 // Disable autonegotiation
enum { MG_PHY_SPEED_10M, MG_PHY_SPEED_100M, MG_PHY_SPEED_1000M };

35
src/drivers/phy.c
View File

@ -1,7 +1,7 @@
#include "phy.h"
enum { // ID1 ID2
MG_PHY_KSZ8x = 0x22, // 0022 1561 - KSZ8081RNB
enum { // ID1 ID2
MG_PHY_KSZ8x = 0x22, // 0022 1561 - KSZ8081RNB
MG_PHY_DP83x = 0x2000,
MG_PHY_DP83867 = 0xa231, // 2000 a231 - TI DP83867I
MG_PHY_DP83825 = 0xa140, // 2000 a140 - TI DP83825I
@ -30,23 +30,15 @@ static const char *mg_phy_id_to_str(uint16_t id1, uint16_t id2) {
switch (id1) {
case MG_PHY_DP83x:
switch (id2) {
case MG_PHY_DP83867:
return "DP83867";
case MG_PHY_DP83848:
return "DP83848";
case MG_PHY_DP83825:
return "DP83825";
default:
return "DP83x";
case MG_PHY_DP83867: return "DP83867";
case MG_PHY_DP83848: return "DP83848";
case MG_PHY_DP83825: return "DP83825";
default: return "DP83x";
}
case MG_PHY_KSZ8x:
return "KSZ8x";
case MG_PHY_LAN87x:
return "LAN87x";
case MG_PHY_RTL8201:
return "RTL8201";
default:
return "unknown";
case MG_PHY_KSZ8x: return "KSZ8x";
case MG_PHY_LAN87x: return "LAN87x";
case MG_PHY_RTL8201: return "RTL8201";
default: return "unknown";
}
(void) id2;
}
@ -61,6 +53,13 @@ void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) {
id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2);
MG_INFO(("PHY ID: %#04x %#04x (%s)", id1, id2, mg_phy_id_to_str(id1, id2)));
if (config & MG_PHY_DISABLE_AUTONEG) {
uint16_t val = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
phy->write_reg(phy_addr, MG_PHY_REG_BCR, val & (uint16_t) ~MG_BIT(12));
val = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
phy->write_reg(phy_addr, MG_PHY_REG_BCR, (uint16_t) MG_BIT(9));
}
if (id1 == MG_PHY_DP83x && id2 == MG_PHY_DP83867) {
phy->write_reg(phy_addr, 0x0d, 0x1f); // write 0x10d to IO_MUX_CFG (0x0170)
phy->write_reg(phy_addr, 0x0e, 0x170);

11
src/drivers/phy.h
View File

@ -7,13 +7,10 @@ struct mg_phy {
void (*write_reg)(uint8_t addr, uint8_t reg, uint16_t value);
};
// PHY configuration settings, bitmask
enum {
// Set if PHY LEDs are connected to ground
MG_PHY_LEDS_ACTIVE_HIGH = (1 << 0),
// Set when PHY clocks MAC. Otherwise, MAC clocks PHY
MG_PHY_CLOCKS_MAC = (1 << 1),
};
// MG_TCPIP_PHY_CONF configuration settings, bitmask of the following:
#define MG_PHY_LEDS_ACTIVE_HIGH 1 // PHY LEDs are connected to ground
#define MG_PHY_CLOCKS_MAC 2 // PHY clocks MAC. Otherwise, MAC clocks PHY
#define MG_PHY_DISABLE_AUTONEG 4 // Disable autonegotiation
enum { MG_PHY_SPEED_10M, MG_PHY_SPEED_100M, MG_PHY_SPEED_1000M };