Merge pull request #2929 from cesanta/xmc7200

move to Wizard

.github/workflows/nightly.yml

@@ -328,6 +328,7 @@ jobs:
       fail-fast: false
       matrix:
         example:
+          - path: infineon/infineon-xmc7200
           - path: nxp/frdm-mcxn947-make-baremetal-builtin
           - path: nxp/frdm-mcxn947-make-freertos-builtin
           - path: nxp/rt1020-evk-make-baremetal-builtin
@@ -436,7 +437,6 @@ jobs:
       matrix:
         ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
         example:
-          - path: infineon/infineon-xmc7200
           - path: microchip/same54-xpro/device-dashboard
           - path: nxp/rt1020-evk-make-freertos-builtin
           - path: nxp/rt1060-evk-make-freertos-builtin

.github/workflows/quicktest.yml

@@ -200,6 +200,7 @@ jobs:
       fail-fast: false
       matrix:
         example:
+          - path: infineon/infineon-xmc7200
           - path: nxp/frdm-mcxn947-make-baremetal-builtin
           - path: nxp/frdm-mcxn947-make-freertos-builtin
           - path: nxp/rt1020-evk-make-baremetal-builtin
@@ -302,7 +303,6 @@ jobs:
       fail-fast: false
       matrix:
         example:
-          - path: infineon/infineon-xmc7200
           - path: microchip/same54-xpro/device-dashboard
           - path: nxp/rt1020-evk-make-freertos-builtin
           - path: nxp/rt1060-evk-make-freertos-builtin

examples/infineon/infineon-xmc7200/Makefile

@@ -1,41 +1,29 @@
-CFLAGS  = -W -Wall -Werror -Wextra  -Wundef -Wshadow -Wdouble-promotion
+BOARD = xmc7200
-CFLAGS += -Wformat-truncation -fno-common # -Wconversion is not SDK-friendly
+IDE = GCC+make
-CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
+RTOS = baremetal
-CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_xmc7/devices/COMPONENT_CAT1C/include/
+WIZARD_URL ?= http://mongoose.ws/wizard
-CFLAGS += -Icmsis_xmc7/devices/COMPONENT_CAT1C/include/ip/
-CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
-LDSCRIPT = link.ld
-LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map 
-
-SOURCES = main.c hal.c startup.c
-CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS	# Make startup code work as expected
-
-# Mongoose options are defined in mongoose_custom.h
-SOURCES += mongoose.c net.c packed_fs.c
-
-# Example specific build options. See README.md
-CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\"
-
-ifeq ($(OS),Windows_NT)
-  RM = cmd /C del /Q /F /S
-else
-  RM = rm -rf
-endif
 
 all build example: firmware.bin
 
-firmware.bin: firmware.elf
+firmware.bin: wizard
-	arm-none-eabi-objcopy -O binary $< $@
+	make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
 
-firmware.elf: cmsis_core cmsis_xmc7 $(SOURCES) hal.h link.ld Makefile
+wizard:
-	arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
+	hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
-	arm-none-eabi-size $@
+	&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
+	unzip wizard.zip
+	cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h
 
-cmsis_core:     # ARM CMSIS core headers
+
-	git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
+# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
-cmsis_xmc7:
+DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/??
-	git clone https://github.com/Infineon/mtb-pdl-cat1.git $@
+update: firmware.bin
-	echo "" > cmsis_xmc7/devices/COMPONENT_CAT1C/include/ip/system_cat1c.h
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
+
+test update: CFLAGS_EXTRA ="-DUART_DEBUG=USART1"
+test: update
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt
+	grep 'READY, IP:' /tmp/output.txt       # Check for network init
 
 clean:
-	$(RM) firmware.* *.su cmsis_core cmsis_xmc7 *.zip
+	rm -rf firmware.* wizard*

examples/infineon/infineon-xmc7200/README.md

@@ -0,0 +1 @@
+See [Wizard](https://mongoose.ws/wizard/#/output?board=xmc7200&ide=GCC+make&rtos=baremetal&file=README.md)

examples/infineon/infineon-xmc7200/hal.c

@@ -1,147 +0,0 @@
-// Copyright (c) 2024 Cesanta Software Limited
-// All rights reserved
-
-#include "hal.h"
-
-static volatile uint64_t s_ticks;  // Milliseconds since boot
-void SysTick_Handler(void) {       // SyStick IRQ handler, triggered every 1ms
-  s_ticks++;
-}
-
-bool mg_random(void *buf, size_t len) {  // Use on-board RNG
-  for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
-    uint32_t r = rng_read();
-    memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
-  }
-  return true;
-}
-
-uint64_t mg_millis(void) {  // Let Mongoose use our uptime function
-  return s_ticks;           // Return number of milliseconds since boot
-}
-
-void hal_init(void) {
-  clock_init();                            // Set system clock to SYS_FREQUENCY
-  SystemCoreClock = SYS_FREQUENCY;         // Update SystemCoreClock global var
-  SysTick_Config(SystemCoreClock / 1000);  // Sys tick every 1ms
-  rng_init();                              // Initialise random number generator
-
-  uart_init(UART_DEBUG, 115200);  // Initialise UART
-  gpio_output(LED1);              // Initialise LED1
-  gpio_output(LED2);              // Initialise LED2
-  gpio_output(LED3);              // Initialise LED3
-  ethernet_init();                // Initialise Ethernet pins
-}
-
-#if defined(__ARMCC_VERSION)
-// Keil specific - implement IO printf redirection
-int fputc(int c, FILE *stream) {
-  if (stream == stdout || stream == stderr) uart_write_byte(UART_DEBUG, c);
-  return c;
-}
-#elif defined(__GNUC__)
-// ARM GCC specific. ARM GCC is shipped with Newlib C library.
-// Implement newlib syscalls:
-//      _sbrk() for malloc
-//      _write() for printf redirection
-//      the rest are just stubs
-#include <sys/stat.h>  // For _fstat()
-
-uint32_t SystemCoreClock;
-void SystemInit(void) {  // Called automatically by startup code
-}
-
-int _fstat(int fd, struct stat *st) {
-  (void) fd, (void) st;
-  return -1;
-}
-
-extern unsigned char _end[];  // End of data section, start of heap. See link.ld
-static unsigned char *s_current_heap_end = _end;
-
-size_t hal_ram_used(void) {
-  return (size_t) (s_current_heap_end - _end);
-}
-
-size_t hal_ram_free(void) {
-  unsigned char endofstack;
-  return (size_t) (&endofstack - s_current_heap_end);
-}
-
-void *_sbrk(int incr) {
-  unsigned char *prev_heap;
-  unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
-  prev_heap = s_current_heap_end;
-  // Check how much space we  got from the heap end to the stack end
-  if (s_current_heap_end + incr > heap_end) return (void *) -1;
-  s_current_heap_end += incr;
-  return prev_heap;
-}
-
-int _open(const char *path) {
-  (void) path;
-  return -1;
-}
-
-int _close(int fd) {
-  (void) fd;
-  return -1;
-}
-
-int _isatty(int fd) {
-  (void) fd;
-  return 1;
-}
-
-int _lseek(int fd, int ptr, int dir) {
-  (void) fd, (void) ptr, (void) dir;
-  return 0;
-}
-
-void _exit(int status) {
-  (void) status;
-  for (;;) asm volatile("BKPT #0");
-}
-
-void _kill(int pid, int sig) {
-  (void) pid, (void) sig;
-}
-
-int _getpid(void) {
-  return -1;
-}
-
-int _write(int fd, char *ptr, int len) {
-  (void) fd, (void) ptr, (void) len;
-  if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
-  return -1;
-}
-
-int _read(int fd, char *ptr, int len) {
-  (void) fd, (void) ptr, (void) len;
-  return -1;
-}
-
-int _link(const char *a, const char *b) {
-  (void) a, (void) b;
-  return -1;
-}
-
-int _unlink(const char *a) {
-  (void) a;
-  return -1;
-}
-
-int _stat(const char *path, struct stat *st) {
-  (void) path, (void) st;
-  return -1;
-}
-
-int mkdir(const char *path, mode_t mode) {
-  (void) path, (void) mode;
-  return -1;
-}
-
-void _init(void) {
-}
-#endif                 // __GNUC__

examples/infineon/infineon-xmc7200/hal.h

@@ -1,244 +0,0 @@
-// Copyright (c) 2023 Cesanta Software Limited
-// All rights reserved
-
-#pragma once
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-
-#define LED1 PIN(16, 1)
-#define LED2 PIN(16, 2)
-#define LED3 PIN(16, 3)
-
-#include "xmc7200d_e272k8384.h"
-
-#define BIT(x) (1UL << (x))
-#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
-#define PIN(bank, num) ((bank << 8) | (num))
-#define PINNO(pin) (pin & 255)
-#define PINBANK(pin) (pin >> 8)
-
-void hal_init(void);
-size_t hal_ram_free(void);
-size_t hal_ram_used(void);
-
-static inline void spin(volatile uint32_t count) {
-  while (count--) (void) 0;
-}
-
-extern uint32_t SystemCoreClock;
-
-enum {PLL_FEEDBACK = 50, PLL_REF = 1, PLL_OUT = 4};
-#define CLK_IMO 8000000UL
-#define SYS_FREQUENCY ((CLK_IMO * PLL_FEEDBACK) / (PLL_REF * PLL_OUT))
-
-#ifndef UART_DEBUG
-#define UART_DEBUG SCB3
-#endif
-
-enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
-enum { GPIO_HIGHZ = 0, GPIO_PULLUP = 2, GPIO_PULLDOWN = 3, GPIO_OPENDRAIN_LOW = 4,
-       GPIO_OPENDRAIN_HIGH = 5, GPIO_STRONG = 6, GPIO_PULLUP_DOWN = 7};
-enum { GPIO_SPEED_LOW = 3, GPIO_SPEED_MEDIUM = 2, GPIO_SPEED_HIGH = 0};
-#undef GPIO
-#define GPIO_TypeDef GPIO_PRT_Type
-#define GPIO(N) ((GPIO_TypeDef *) (GPIO_BASE + 0x80 * (N)))
-
-static GPIO_TypeDef *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
-
-static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
-                             uint8_t speed, uint8_t pull, uint8_t af) {
-	(void) pin, (void) mode, (void) type, (void) speed, (void) pull, (void) af;
-  GPIO_TypeDef *gpio = gpio_bank(pin);
-  uint8_t pinno = PINNO(pin);
-  uint32_t msk, pos;
-
-  // configure input / output direction
-  if (mode == GPIO_MODE_INPUT) {
-    gpio->CFG |= 1 << (4 * pinno + 3); // enable input buffer (IN_ENx)
-  }
-
-  if (af || (mode == GPIO_MODE_AF && af)) {
-    // configure alternate function
-    HSIOM_PRT_Type* hsiom = ((HSIOM_PRT_Type*) HSIOM) + PINBANK(pin);
-    volatile uint32_t *port_sel = pinno < 4 ? &hsiom->PORT_SEL0 : &hsiom->PORT_SEL1;
-    pos = 8 * (pinno % 4), msk = 0x1f << pos;
-    *port_sel &= ~msk, *port_sel |= af << pos;
-  }
-
-  // configure driver mode
-  msk = 7, pos = 4 * pinno;
-  CLRSET(gpio->CFG, msk << pos, type << pos);
-
-  // configure speed
-  msk = 3, pos = 2 * pinno + 16;
-  CLRSET(gpio->CFG_OUT, msk << pos, speed << pos);
-
-  if (mode == GPIO_MODE_OUTPUT /*&& af == 0*/) {
-    gpio->OUT_SET = (1 << pinno);
-  }
-}
-
-static inline void gpio_input(uint16_t pin) {
-	gpio_init(pin, GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH,
-	            0, 0);
-}
-
-static inline void gpio_output(uint16_t pin) {
-	gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_MEDIUM,
-	            0, 0);
-}
-
-static inline bool gpio_read(uint16_t pin) {
-  GPIO_TypeDef *gpio = gpio_bank(pin);
-  uint8_t pinno = PINNO(pin);
-  if (gpio->CFG & (1 << (4 * pinno + 3))) {
-    // pin mode is input, reading from GPIO_PRT_IN
-    return gpio->IN & (1 << pinno);
-  } else {
-    // pin mode is output, reading from GPIO_PRT_OUT
-    return gpio->OUT & (1 << pinno);
-  }
-}
-
-static inline void gpio_write(uint16_t pin, bool value) {
-	GPIO_TypeDef *gpio = gpio_bank(pin);
-  uint8_t pinno = PINNO(pin);
-  if (value) {
-    gpio->OUT_SET = 1 << pinno;
-  } else {
-    gpio->OUT_CLR = 1 << pinno;
-  }
-}
-
-static inline void gpio_toggle(uint16_t pin) {
-  gpio_write(pin, !gpio_read(pin));
-}
-
-static inline void uart_init(volatile CySCB_Type *uart, unsigned long baud) {
-  (void) uart, (void) baud;
-  uint16_t rx = 0, tx = 0;
-  if (uart == SCB3) {
-    rx = PIN(13, 0), tx = PIN(13, 1);
-  } else {
-    return; // unsupported uart
-  }
-
-  // set pins
-  gpio_init(rx, GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 17);
-  gpio_init(tx, GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 17);
-
-  // enable peripheral clock (18.6.2)
-  // compute divider first (we choose 24 bit divider 0)
-  unsigned long div = 0, frac = 0, ovs = 16;
-  div = SYS_FREQUENCY / (baud * ovs);
-  if (div == 0) div = 1;
-  frac = SYS_FREQUENCY % (baud * ovs);
-  frac = (frac * 100) / (baud * ovs);
-  PERI_PCLK->GR[1].DIV_CMD = (3 << PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos) |
-                             PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk |
-                             PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk;
-  PERI_PCLK->GR[1].DIV_CMD |= PERI_PCLK_GR_DIV_CMD_DISABLE_Msk; // disable divider
-  PERI_PCLK->GR[1].DIV_24_5_CTL[0] = (((uint8_t) (div - 1)) << PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Pos) |
-                                     (frac << PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Pos);
-  PERI_PCLK->GR[1].DIV_CMD = (3 << PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos) |
-                             PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk |
-                             PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk;;
-  PERI_PCLK->GR[1].DIV_CMD |= PERI_PCLK_GR_DIV_CMD_ENABLE_Msk; // enable divider
-  PERI_PCLK->GR[1].CLOCK_CTL[PCLK_SCB3_CLOCK & 0xff] = 3 << PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Pos;  // connect SCB3 to div_24_5_ctl[0]
-
-  // configure UART interface
-  uart->CTRL = ((ovs - 1) << SCB_CTRL_OVS_Pos) | (2 << SCB_CTRL_MODE_Pos);
-  uart->UART_CTRL = 0;
-  uart->UART_RX_CTRL = 1 << SCB_UART_RX_CTRL_STOP_BITS_Pos;
-  uart->RX_CTRL = 7 << SCB_RX_CTRL_DATA_WIDTH_Pos;
-  uart->UART_TX_CTRL = 1 << SCB_UART_TX_CTRL_STOP_BITS_Pos;
-  uart->TX_CTRL = 7 << SCB_TX_CTRL_DATA_WIDTH_Pos;
-  uart->TX_FIFO_CTRL = 1 << 16;
-  uart->TX_FIFO_CTRL = 0;
-  uart->CTRL |= 1 << SCB_CTRL_ENABLED_Pos;
-}
-
-static inline void uart_write_byte(volatile CySCB_Type *uart, uint8_t byte) {
-  (void) byte; (void) uart;
-  while((uart->INTR_TX & SCB_INTR_TX_EMPTY_Msk) == 0) spin(1);
-  uart->TX_FIFO_WR = byte;
-  uart->INTR_TX |= ~SCB_INTR_TX_EMPTY_Msk;
-}
-
-static inline void uart_write_buf(volatile CySCB_Type *uart, char *buf, size_t len) {
-	while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
-}
-
-static inline void rng_init(void) {
-}
-static inline uint32_t rng_read(void) {
-   return 0;
-}
-
-static inline void ethernet_init(void) {
-  gpio_init(PIN(26, 0), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_REF_CLK
-  gpio_init(PIN(26, 1), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TX_CTL
-  gpio_init(PIN(26, 2), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TX_CLK
-  gpio_init(PIN(26, 3), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_0
-  gpio_init(PIN(26, 4), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_1
-  gpio_init(PIN(26, 5), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_2
-  gpio_init(PIN(26, 6), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_3
-  gpio_init(PIN(26, 7), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_0
-
-  gpio_init(PIN(27, 0), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_1
-  gpio_init(PIN(27, 1), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_2
-  gpio_init(PIN(27, 2), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_3
-  gpio_init(PIN(27, 3), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RX_CTL
-  gpio_init(PIN(27, 4), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RX_CLK
-  gpio_init(PIN(27, 5), GPIO_MODE_INPUT, GPIO_STRONG, GPIO_SPEED_LOW, 0, 27); // ETH1_MDIO
-  gpio_init(PIN(27, 6), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_LOW, 0, 27); // ETH1_MDC
-  //gpio_init(PIN(27, 7), GPIO_MODE_OUTPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 0); // ETH1_RST
-
-  CPUSS->CM7_0_SYSTEM_INT_CTL[eth_1_interrupt_eth_0_IRQn] = 0x80000003; // assign CPU interrupt #3
-  NVIC->ISER[0] = 1 << 3;
-
-  spin(10000000); // artificial delay to wait for PHY init
-}
-
-static inline void clock_init(void) {
-  SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));  // Enable FPU
-  asm("DSB");
-  asm("ISB");
-  
-  // configure PLL
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_BYPASS_SEL_Msk, BIT(29)); // First bypass PLL
-  spin(10);
-  SRSS->CLK_PLL400M[0].CONFIG &= ~CLK_PLL400M_CONFIG_ENABLE_Msk; // disable the PLL itself
-
-  // IMO source generates a frequency of 8MHz. The final frequency will be
-  // calculated as (CLK_IMO * feedback) / (reference * output_div)
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_FEEDBACK_DIV_Msk, PLL_FEEDBACK << CLK_PLL400M_CONFIG_FEEDBACK_DIV_Pos);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_REFERENCE_DIV_Msk, PLL_REF << CLK_PLL400M_CONFIG_REFERENCE_DIV_Pos);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_OUTPUT_DIV_Msk, PLL_OUT << CLK_PLL400M_CONFIG_OUTPUT_DIV_Pos);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG2, CLK_PLL400M_CONFIG2_FRAC_DIV_Msk, 0);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG2, CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Msk, 0);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG2, CLK_PLL400M_CONFIG2_FRAC_EN_Msk, 1 << CLK_PLL400M_CONFIG2_FRAC_EN_Pos);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_BYPASS_SEL_Msk, 0);
-  spin(10);
-  SRSS->CLK_PLL400M[0].CONFIG |= CLK_PLL400M_CONFIG_ENABLE_Msk; // enable the PLL
-  while (SRSS->CLK_PLL400M[0].CONFIG & 1) spin(1);
-
-  // configure PATH1 with source set to IMO
-  SRSS->CLK_PATH_SELECT[1] = 0;
-
-  // enable CLK_HFx
-  uint8_t clocks[] = {0, 1, 2, 3, 4, 5, 6};
-  for (size_t i = 0; i < sizeof(clocks) / sizeof(uint8_t); i++) {
-    CLRSET(SRSS->CLK_ROOT_SELECT[clocks[i]], SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk, 1); // choose PATH1
-    CLRSET(SRSS->CLK_ROOT_SELECT[clocks[i]], SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Msk, 1 << SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Pos);
-    if (clocks[i] != 0) // CLF_HF0 is already enabled
-      SRSS->CLK_ROOT_SELECT[clocks[i]] |= SRSS_CLK_ROOT_SELECT_ENABLE_Msk; // enable clock root
-  }
-
-  // set systick frequency
-  uint32_t tenms = SYS_FREQUENCY / 100 - 1; // number of cycles executed in 10ms
-  CPUSS->SYSTICK_CTL = tenms | (3 << CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos); // select CLK_HF as source
-}

examples/infineon/infineon-xmc7200/link.ld

@@ -1,31 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(Reset_Handler)
-
-MEMORY
-{
-    flash(RX) : ORIGIN = 0x10080000, LENGTH = 0x80000
-    sram(!RX) : ORIGIN = 0x28000800, LENGTH = 510K
-}
-
-_estack     = ORIGIN(sram) + LENGTH(sram);
-
-SECTIONS
-{ 
-    .vectors  : { . = ALIGN(4); KEEP(*(.vectors)); . = ALIGN(4); } > flash
-    .text     : { *(.text*) } > flash
-    .rodata   : { *(.rodata*) } > flash
-
-    .data : {
-        _sdata = .;
-        *(.first_data)
-        *(.data SORT(.data.*))
-        _edata = .;
-    } > sram AT > flash
-    _sidata = LOADADDR(.data);
-
-    .bss : { _sbss = .; *(.bss SORT(.bss.*) COMMON) _ebss = .; } > sram
-
-    . = ALIGN(8);
-    _end = .;
-}

examples/infineon/infineon-xmc7200/main.c

@@ -1,32 +0,0 @@
-// Copyright (c) 2024 Cesanta Software Limited
-// All rights reserved
-
-#include "hal.h"
-#include "mongoose.h"
-#include "net.h"
-
-#define BLINK_PERIOD_MS 1000
-
-static void timer_fn(void *arg) {
-  gpio_toggle(LED1);  // Blink LED
-  (void) arg;         // Unused
-}
-
-int main(void) {
-  struct mg_mgr mgr;  // Mongoose event manager
-
-  hal_init();  // Cross-platform hardware init
-  
-  mg_mgr_init(&mgr);        // Initialise it
-  mg_log_set(MG_LL_DEBUG);  // Set log level to debug
-  mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mgr);
-
-  MG_INFO(("Initialising application..."));
-  web_init(&mgr);
-
-  for (;;) {
-    mg_mgr_poll(&mgr, 0);
-  }
-
-  return 0;
-}

examples/infineon/infineon-xmc7200/mongoose.c

@@ -1 +0,0 @@
-../../../mongoose.c

examples/infineon/infineon-xmc7200/mongoose.h

@@ -1 +0,0 @@
-../../../mongoose.h

examples/infineon/infineon-xmc7200/mongoose_config.h

@@ -1,26 +0,0 @@
-#pragma once
-
-// See https://mongoose.ws/documentation/#build-options
-#define MG_ARCH MG_ARCH_NEWLIB
-
-#define MG_ENABLE_TCPIP 1
-#define MG_ENABLE_DRIVER_XMC7 1
-#define MG_IO_SIZE 256
-#define MG_ENABLE_CUSTOM_MILLIS 1
-#define MG_ENABLE_CUSTOM_RANDOM 1
-#define MG_ENABLE_PACKED_FS 1
-
-// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
-// By default, those are set to zero, meaning that DHCP is used
-//
-// #define MG_TCPIP_IP MG_IPV4(192, 168, 1, 10)
-// #define MG_TCPIP_GW MG_IPV4(192, 168, 1, 1)
-// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
-
-// Set custom MAC address. By default, it is randomly generated
-// Using a build-time constant:
-// #define MG_SET_MAC_ADDRESS(mac) do { uint8_t buf_[6] = {2,3,4,5,6,7}; memmove(mac, buf_, sizeof(buf_)); } while (0)
-//
-// Using custom function:
-// extern void my_function(unsigned char *mac);
-// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)

examples/infineon/infineon-xmc7200/net.c

@@ -1 +0,0 @@
-../../device-dashboard/net.c

examples/infineon/infineon-xmc7200/net.h

@@ -1 +0,0 @@
-../../device-dashboard/net.h

examples/infineon/infineon-xmc7200/packed_fs.c

@@ -1 +0,0 @@
-../../device-dashboard/packed_fs.c

examples/infineon/infineon-xmc7200/startup.c

@@ -1,83 +0,0 @@
-#include "xmc7200d_e272k8384.h"
-
-void Reset_Handler(void);    // Defined below
-void Dummy_Handler(void);    // Defined below
-void SysTick_Handler(void);  // Defined in main.c
-void SystemInit(void);       // Defined in main.c, called by reset handler
-void _estack(void);          // Defined in link.ld
-
-#define WEAK_ALIAS __attribute__((weak, alias("Default_Handler")))
-
-WEAK_ALIAS void NMI_Handler(void);
-WEAK_ALIAS void HardFault_Handler(void);
-WEAK_ALIAS void SVCall_Handler(void);
-WEAK_ALIAS void PendSV_Handler(void);
-WEAK_ALIAS void SysTick_Handler(void);
-
-WEAK_ALIAS void Default_Intr_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr0_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr1_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr2_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr4_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr5_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr6_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr7_Handler(void);
-WEAK_ALIAS void ETH_IRQHandler(void);
-
-void CM0P_CpuIntr3_Handler(void) {
-	ETH_IRQHandler();
-}
-
-__attribute__((section(".vectors"))) void (*const tab[16 + 16])(void) = {
-	_estack,
-	Reset_Handler,
-	NMI_Handler,
-	HardFault_Handler,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	SVCall_Handler,
-	0,
-	0,
-	PendSV_Handler,
-	SysTick_Handler,
-	CM0P_CpuIntr0_Handler,
-	CM0P_CpuIntr1_Handler,
-	CM0P_CpuIntr2_Handler,
-	CM0P_CpuIntr3_Handler,
-	CM0P_CpuIntr4_Handler,
-	CM0P_CpuIntr5_Handler,
-	CM0P_CpuIntr6_Handler,
-	CM0P_CpuIntr7_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler
-};
-
-__attribute__((naked, noreturn)) void Reset_Handler(void) {
-  // Clear BSS section, and copy data section from flash to RAM
-  extern long _sbss, _ebss, _sdata, _edata, _sidata;
-  for (long *src = &_sbss; src < &_ebss; src++) *src = 0;
-  for (long *src = &_sdata, *dst = &_sidata; src < &_edata;) *src++ = *dst++;
-
-  SCB->VTOR = (uint32_t) &tab;
-  SystemInit();
-
-  // Call main()
-  extern void main(void);
-  main();
-  for (;;) (void) 0;  // Infinite loop
-}
-
-void Default_Handler(void) {
-  for (;;) (void) 0;
-}