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Merge pull request #1701 from cesanta/enableFPU

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Enable FPU
This commit is contained in:
Sergey Lyubka 2022-09-02 15:46:00 +01:00 committed by GitHub
commit 51076e68c8
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 8 additions and 4 deletions
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2
examples/stm32/nucleo-f429zi-baremetal/Makefile
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@ -8,7 +8,7 @@ CFLAGS ?= -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \
-g3 -Os -ffunction-sections -fdata-sections -I. -I$(ROOT) \ -g3 -Os -ffunction-sections -fdata-sections -I. -I$(ROOT) \
-DMG_ARCH=MG_ARCH_NEWLIB -DMIP_DEBUG=1 -DMG_ENABLE_PACKED_FS=1 \ -DMG_ARCH=MG_ARCH_NEWLIB -DMIP_DEBUG=1 -DMG_ENABLE_PACKED_FS=1 \
-DMG_ENABLE_CUSTOM_MILLIS=1 -DxMG_ENABLE_LINES=1 -DMG_ENABLE_MIP=1 \ -DMG_ENABLE_CUSTOM_MILLIS=1 -DxMG_ENABLE_LINES=1 -DMG_ENABLE_MIP=1 \
-mcpu=cortex-m4 -mthumb -mfloat-abi=soft $(EXTRA_CFLAGS) -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 $(EXTRA_CFLAGS)
LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
SOURCES = boot.c main.c syscalls.c \ SOURCES = boot.c main.c syscalls.c \
$(ROOT)/mongoose.c \ $(ROOT)/mongoose.c \

4
examples/stm32/nucleo-f429zi-baremetal/mcu.h
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@ -203,8 +203,10 @@ static inline void clock_init(void) { // Set clock frequency
while ((PWR->CSR & BIT(16)) == 0) spin(1); // Wait until done while ((PWR->CSR & BIT(16)) == 0) spin(1); // Wait until done
PWR->CR |= BIT(17); // Enable overdrive switching PWR->CR |= BIT(17); // Enable overdrive switching
while ((PWR->CSR & BIT(17)) == 0) spin(1); // Wait until done while ((PWR->CSR & BIT(17)) == 0) spin(1); // Wait until done
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
#endif #endif
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
asm ("DSB");
asm ("ISB");
FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch, Icache, Dcache FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch, Icache, Dcache
RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers
RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P

2
examples/stm32/nucleo-f746zg-baremetal/Makefile
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@ -8,7 +8,7 @@ CFLAGS ?= -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \
-g3 -Os -ffunction-sections -fdata-sections -I. -I$(ROOT) \ -g3 -Os -ffunction-sections -fdata-sections -I. -I$(ROOT) \
-DMG_ARCH=MG_ARCH_NEWLIB -DMIP_DEBUG=1 -DMG_ENABLE_PACKED_FS=1 \ -DMG_ARCH=MG_ARCH_NEWLIB -DMIP_DEBUG=1 -DMG_ENABLE_PACKED_FS=1 \
-DMG_ENABLE_CUSTOM_MILLIS=1 -DxMG_ENABLE_LINES=1 -DMG_ENABLE_MIP=1 \ -DMG_ENABLE_CUSTOM_MILLIS=1 -DxMG_ENABLE_LINES=1 -DMG_ENABLE_MIP=1 \
-mcpu=cortex-m7 -mthumb -mfloat-abi=soft $(EXTRA_CFLAGS) -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 $(EXTRA_CFLAGS)
LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
SOURCES = boot.c main.c syscalls.c \ SOURCES = boot.c main.c syscalls.c \
$(ROOT)/mongoose.c \ $(ROOT)/mongoose.c \

4
examples/stm32/nucleo-f746zg-baremetal/mcu.h
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@ -203,8 +203,10 @@ static inline void clock_init(void) { // Set clock frequency
while ((PWR->CSR1 & BIT(16)) == 0) spin(1); // Wait until done while ((PWR->CSR1 & BIT(16)) == 0) spin(1); // Wait until done
PWR->CR1 |= BIT(17); // Enable overdrive switching PWR->CR1 |= BIT(17); // Enable overdrive switching
while ((PWR->CSR1 & BIT(17)) == 0) spin(1); // Wait until done while ((PWR->CSR1 & BIT(17)) == 0) spin(1); // Wait until done
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
#endif #endif
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
asm ("DSB");
asm ("ISB");
FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch
RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers
RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P