From 8a8d5ce151b1ede4c59a3c20594e2d222159f5df Mon Sep 17 00:00:00 2001 From: "Sergio R. Caprile" Date: Mon, 9 Oct 2023 16:43:30 -0300 Subject: [PATCH] Add FreeRTOS example for RT1020 --- .github/workflows/test.yml | 3 + .../Makefile | 6 +- .../FreeRTOSConfig.h | 38 +++ .../rt1020-evk-make-freertos-builtin/Makefile | 69 ++++ .../rt1020-evk-make-freertos-builtin/hal.h | 303 ++++++++++++++++++ .../link_ram.ld | 16 + .../rt1020-evk-make-freertos-builtin/main.c | 96 ++++++ .../mongoose.c | 1 + .../mongoose.h | 1 + .../mongoose_custom.h | 12 + .../syscalls.c | 85 +++++ .../sysinit.c | 106 ++++++ 12 files changed, 732 insertions(+), 4 deletions(-) create mode 100644 examples/nxp/rt1020-evk-make-freertos-builtin/FreeRTOSConfig.h create mode 100644 examples/nxp/rt1020-evk-make-freertos-builtin/Makefile create mode 100644 examples/nxp/rt1020-evk-make-freertos-builtin/hal.h create mode 100644 examples/nxp/rt1020-evk-make-freertos-builtin/link_ram.ld create mode 100644 examples/nxp/rt1020-evk-make-freertos-builtin/main.c create mode 120000 examples/nxp/rt1020-evk-make-freertos-builtin/mongoose.c create mode 120000 examples/nxp/rt1020-evk-make-freertos-builtin/mongoose.h create mode 100644 examples/nxp/rt1020-evk-make-freertos-builtin/mongoose_custom.h create mode 100644 examples/nxp/rt1020-evk-make-freertos-builtin/syscalls.c create mode 100644 examples/nxp/rt1020-evk-make-freertos-builtin/sysinit.c diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index ca07cd76..888e40bb 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -232,6 +232,8 @@ jobs: run: sudo apt -y update; sudo apt -y install gcc-arm-none-eabi - if: ${{ env.GO == 1 }} run: make -C examples/nxp/rt1020-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}} + - if: ${{ env.GO == 1 }} + run: make -C examples/nxp/rt1020-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}} test_tm4c: runs-on: ubuntu-latest @@ -315,6 +317,7 @@ jobs: - path: nxp/nxp-lpcxpresso54618-lwip-freertos - path: nxp/nxp-lpcxpresso54628-lwip-freertos - path: nxp/rt1020-evk-make-baremetal-builtin + - path: nxp/rt1020-evk-make-freertos-builtin - path: nxp/nxp-twrk65f180m-lwip-freertos - path: nxp/nxp-twrkv58f220m-lwip-freertos - path: rp2040/pico-rmii diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile b/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile index 89a0216f..9e04601f 100644 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile +++ b/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile @@ -6,7 +6,7 @@ CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 LDFLAGS ?= -Tlink_ram.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map SOURCES = main.c syscalls.c sysinit.c -SOURCES += cmsis_mcu/devices/MIMXRT1021/gcc/startup_MIMXRT1021.S +SOURCES += cmsis_mcu/devices/MIMXRT1021/gcc/startup_MIMXRT1021.S # NXP startup file. Compiler-dependent! CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS # Make startup code work as expected # Mongoose-specific. See https://mongoose.ws/documentation/#build-options @@ -30,7 +30,7 @@ all build example: firmware.bin firmware.bin: firmware.elf arm-none-eabi-objcopy -O binary $< $@ -firmware.elf: cmsis_core cmsis_mcu $(SOURCES) hal.h link.ld Makefile +firmware.elf: cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld Makefile arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@ arm-none-eabi-size $@ @@ -42,8 +42,6 @@ cmsis_core: # ARM CMSIS core headers cmsis_mcu: curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.17.0.0.pack -o $@.zip mkdir $@ && cd $@ && unzip -q ../$@.zip -# https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.EVK-MIMXRT1020_BSP.17.0.0.pack -# https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.17.0.0.pack mbedtls: # mbedTLS library git clone --depth 1 -b v2.28.2 https://github.com/mbed-tls/mbedtls $@ diff --git a/examples/nxp/rt1020-evk-make-freertos-builtin/FreeRTOSConfig.h b/examples/nxp/rt1020-evk-make-freertos-builtin/FreeRTOSConfig.h new file mode 100644 index 00000000..24a5b4b6 --- /dev/null +++ b/examples/nxp/rt1020-evk-make-freertos-builtin/FreeRTOSConfig.h @@ -0,0 +1,38 @@ +#pragma once + +#include "hal.h" + +#define configUSE_PREEMPTION 1 +#define configCPU_CLOCK_HZ SYS_FREQUENCY +#define configTICK_RATE_HZ 1000 +#define configMAX_PRIORITIES 5 +#define configUSE_16_BIT_TICKS 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TIMERS 0 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configMINIMAL_STACK_SIZE 128 +#define configTOTAL_HEAP_SIZE (1024 * 32) +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 // trying + +#ifdef __NVIC_PRIO_BITS +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 +#endif +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 +#define configKERNEL_INTERRUPT_PRIORITY \ + (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +#define configMAX_SYSCALL_INTERRUPT_PRIORITY \ + (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +#define configASSERT(expr) \ + if (!(expr)) printf("FAILURE %s:%d: %s\n", __FILE__, __LINE__, #expr) + +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler diff --git a/examples/nxp/rt1020-evk-make-freertos-builtin/Makefile b/examples/nxp/rt1020-evk-make-freertos-builtin/Makefile new file mode 100644 index 00000000..db7f9b45 --- /dev/null +++ b/examples/nxp/rt1020-evk-make-freertos-builtin/Makefile @@ -0,0 +1,69 @@ +CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion +CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion +CFLAGS += -g3 -Os -ffunction-sections -fdata-sections +CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MIMXRT1021 #-DCPU_MIMXRT1021DAG5A +CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 +LDFLAGS ?= -Tlink_ram.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map + +SOURCES = main.c syscalls.c sysinit.c +SOURCES += cmsis_mcu/devices/MIMXRT1021/gcc/startup_MIMXRT1021.S # NXP startup file. Compiler-dependent! +CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS # Make startup code work as expected + +# FreeRTOS. RT1020 has a Cortex-M7 r1p2 core, FreeRTOS recommends using CM4F port for non-r0p1 CM7 micros +SOURCES += FreeRTOS-Kernel/portable/MemMang/heap_4.c +SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c +CFLAGS += -IFreeRTOS-Kernel/include +CFLAGS += -IFreeRTOS-Kernel/portable/GCC/ARM_CM4F -Wno-conversion + +SOURCES += mongoose.c +CFLAGS += $(CFLAGS_EXTRA) # Mongoose options are defined in mongoose_custom.h + +# Example specific build options. See README.md +CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" + +ifeq ($(OS),Windows_NT) + RM = cmd /C del /Q /F /S +else + RM = rm -rf +endif + +all build example: firmware.bin + +firmware.bin: firmware.elf + arm-none-eabi-objcopy -O binary $< $@ + +firmware.elf: FreeRTOS-Kernel cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld mongoose_custom.h + arm-none-eabi-gcc $(SOURCES) $(wildcard FreeRTOS-Kernel/*.c) $(CFLAGS) $(LDFLAGS) -o $@ + +flash: firmware.bin + st-flash --reset write $< 0x8000000 + +cmsis_core: # ARM CMSIS core headers + git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@ +cmsis_mcu: + curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.17.0.0.pack -o $@.zip + mkdir $@ && cd $@ && unzip -q ../$@.zip +FreeRTOS-Kernel: # FreeRTOS sources + git clone --depth 1 -b V10.5.0 https://github.com/FreeRTOS/FreeRTOS-Kernel $@ + +# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/ +DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/4 +update: firmware.bin + curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$< + curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}' + curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1 wm,e000ed0c,5fa0004"}' + curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}' + PC=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,4"}' | jq -r .resp[5:]` && \ + SP=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,0"}' | jq -r .resp[5:]` && \ + REQ="wm,e000ed08,0 wr,d,$$SP wr,f,$$PC" && \ + curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"'"$$REQ"'"}' + curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0001"}' + +test update: CFLAGS += -DUART_DEBUG=LPUART2 +test: update + curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt + grep 'READY, IP:' /tmp/output.txt # Check for network init +# grep 'MQTT connected' /tmp/output.txt # Check for MQTT connection success + +clean: + $(RM) firmware.* *.su cmsis_core cmsis_mcu FreeRTOS-Kernel *.zip diff --git a/examples/nxp/rt1020-evk-make-freertos-builtin/hal.h b/examples/nxp/rt1020-evk-make-freertos-builtin/hal.h new file mode 100644 index 00000000..a2ab9729 --- /dev/null +++ b/examples/nxp/rt1020-evk-make-freertos-builtin/hal.h @@ -0,0 +1,303 @@ +// Copyright (c) 2023 Cesanta Software Limited +// All rights reserved +// https://www.nxp.com/webapp/Download?colCode=IMXRT1020RM +// https://cache.nxp.com/secured/assets/documents/en/user-guide/MIMXRT1020EVKHUG.pdf + +#pragma once + +#include "MIMXRT1021.h" + +#include +#include +#include +#include + +#define BIT(x) (1UL << (x)) +#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK) +#define PIN(bank, num) ((((bank) - '0') << 8) | (num)) +#define PINNO(pin) (pin & 255) +#define PINBANK(pin) (pin >> 8) + +// Use LED for blinking, GPIO_AD_B0_05. GPIO1.5 (schematics) +#define LED PIN('1', 5) + +#ifndef UART_DEBUG +#define UART_DEBUG LPUART1 +#endif + +// No settable constants, see sysinit.c +#define SYS_FREQUENCY 500000000UL + +static inline void spin(volatile uint32_t count) { + while (count--) (void) 0; +} + +enum { CLOCK_OFF = 0U, CLOCK_ON_RUN = 1U, CLOCK_ON_RUN_WAIT = 3U }; +static inline void clock_periph(uint32_t index, uint32_t shift, uint32_t val) { + volatile uint32_t *r = &CCM->CCGR0; + SETBITS(r[index], 3UL << shift, val << shift); +} + +// which peripheral feeds the pin +static inline void gpio_mux_config(uint16_t index, uint8_t af) { + IOMUXC->SW_MUX_CTL_PAD[index] = af; +} + +// which pin feeds the peripheral (2nd stage) +static inline void periph_mux_config(uint16_t index, uint8_t in) { + IOMUXC->SELECT_INPUT[index] = in; +} + +enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT }; +enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN }; +enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH }; +enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP }; +static inline GPIO_Type *gpio_bank(uint16_t pin) { + static const GPIO_Type *g[] = {NULL, GPIO1, GPIO2, GPIO3, NULL, GPIO5}; + return (GPIO_Type *) g[PINBANK(pin)]; +} + +// pin driver/pull-up/down configuration (ignore "keeper") +static inline void gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed, + uint8_t pull) { + bool dopull = pull > 0; + if (dopull) --pull; + IOMUXC->SW_PAD_CTL_PAD[index] = + IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_ODE(type) | + IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH) | + IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PKE(dopull) | + IOMUXC_SW_PAD_CTL_PAD_PUS(pull) | IOMUXC_SW_PAD_CTL_PAD_DSE(7); +} + +static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type, + uint8_t speed, uint8_t pull) { + GPIO_Type *gpio = gpio_bank(pin); + uint8_t bit = (uint8_t) PINNO(pin); + uint32_t mask = (uint32_t) BIT(PINNO(pin)); + + clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s + switch (PINBANK(pin)) { + case 1: + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 + bit, 5); + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 + bit, type, speed, + pull); + clock_periph(1, CCM_CCGR1_CG13_SHIFT, CLOCK_ON_RUN_WAIT); + break; + case 2: + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 + bit, 5); + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 + bit, type, speed, + pull); + clock_periph(0, CCM_CCGR0_CG15_SHIFT, CLOCK_ON_RUN_WAIT); + break; + case 3: + gpio_mux_config(bit < 13 + ? kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 + bit + : kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 + bit - 13, + 5); + gpio_pad_config(bit < 13 + ? kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 + bit + : kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 + bit - 13, + type, speed, pull); + clock_periph(2, CCM_CCGR2_CG13_SHIFT, CLOCK_ON_RUN_WAIT); + break; + case 5: + // TODO(): support sw_mux + clock_periph(1, CCM_CCGR1_CG15_SHIFT, CLOCK_ON_RUN_WAIT); + break; + default: + break; + } + + gpio->IMR &= ~mask; + if (mode == GPIO_MODE_INPUT) { + gpio->GDIR &= ~mask; + } else { + gpio->GDIR |= mask; + } +} +static inline void gpio_input(uint16_t pin) { + gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, + GPIO_PULL_NONE); +} +static inline void gpio_output(uint16_t pin) { + gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, + GPIO_PULL_NONE); +} + +static inline bool gpio_read(uint16_t pin) { + GPIO_Type *gpio = gpio_bank(pin); + uint32_t mask = (uint32_t) BIT(PINNO(pin)); + return gpio->DR & mask; +} +static inline void gpio_write(uint16_t pin, bool value) { + GPIO_Type *gpio = gpio_bank(pin); + uint32_t mask = (uint32_t) BIT(PINNO(pin)); + if (value) { + gpio->DR |= mask; + } else { + gpio->DR &= ~mask; + } +} +static inline void gpio_toggle(uint16_t pin) { + gpio_write(pin, !gpio_read(pin)); +} + +// 14.5 Table 14-4: uart_clk_root +// see sysinit.c for clocks, (14.7.9: defaults to PLL3/6/1 = 80MHz) +static inline void uart_init(LPUART_Type *uart, unsigned long baud) { + uint8_t af = 2; // Alternate function + uint16_t mr = 0, pr = 0, mt = 0, pt = 0; // pins + uint32_t freq = 80000000; // uart_clk_root frequency + if (uart == LPUART1) + mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06, + pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06, + mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07, + pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07; + if (uart == LPUART2) + mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08, + pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08, + mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09, + pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09; + + if (uart == LPUART1) clock_periph(5, CCM_CCGR5_CG12_SHIFT, CLOCK_ON_RUN_WAIT); + if (uart == LPUART2) clock_periph(0, CCM_CCGR0_CG14_SHIFT, CLOCK_ON_RUN_WAIT); + clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s + gpio_mux_config(mt, af); + gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); + gpio_mux_config(mr, af); + gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); + + uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults + uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; + SETBITS(uart->BAUD, + LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK, + LPUART_BAUD_OSR(16 - 1) | + LPUART_BAUD_SBR(freq / (16 * baud))); // Rx sample at 16x + SETBITS(uart->CTRL, + LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | + LPUART_CTRL_IDLECFG_MASK, + LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) | + LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit + uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK; +} + +static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) { + uart->DATA = byte; + while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1); +} +static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) { + while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++); +} +static inline int uart_read_ready(LPUART_Type *uart) { + (void) uart; + return uart->STAT & LPUART_STAT_RDRF_MASK; +} +static inline uint8_t uart_read_byte(LPUART_Type *uart) { + return (uint8_t) (uart->DATA & 255); +} + +static inline void rng_init(void) { + clock_periph(6, CCM_CCGR6_CG6_SHIFT, CLOCK_ON_RUN_WAIT); // trng_clk + SETBITS(TRNG->MCTL, + TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK | TRNG_MCTL_RST_DEF_MASK, + TRNG_MCTL_PRGM(1) | TRNG_MCTL_ERR(1) | + TRNG_MCTL_RST_DEF(1)); // reset to default values + SETBITS(TRNG->MCTL, TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK, + TRNG_MCTL_PRGM(0)); // set to run mode + (void) TRNG->ENT[TRNG_ENT_COUNT - 1]; // start new entropy generation + (void) TRNG->ENT[0]; // defect workaround +} +static inline uint32_t rng_read(void) { + static uint8_t idx = 0; + while ((TRNG->MCTL & TRNG_MCTL_ENT_VAL_MASK) == 0) (void) 0; + uint32_t data = TRNG->ENT[idx++]; // read data + idx %= TRNG_ENT_COUNT; // stay within array limits + if (idx == 0) // we've just read TRNG_ENT_COUNT - 1 + (void) TRNG->ENT[0]; // defect workaround + return data; +} + +// - PHY has no xtal, XI driven from ENET_REF_CLK1 (labeled as ENET_TX_CLK +// (GPIO_AD_B0_08)), generated by the MCU +// - PHY RST connected to GPIO1.4 (GPIO_AD_B0_04); INTRP/NAND_TREE connected to +// GPIO1.22 (GPIO_AD_B1_06) +// - 37.4 REF_CLK1 is RMII mode reference clock for Rx, Tx, and SMI; it is I/O +// - 11.4.2 IOMUXC_GPR_GPR1 bit 17: ENET_REF_CLK_DIR --> 1 ENET_REF_CLK is +// output driven by ref_enetpll0 +// - 14.6.1.3.4 Ethernet PLL (PLL6) +static inline void ethernet_init(void) { + gpio_init(PIN('1', 4), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_MEDIUM, GPIO_PULL_UP); // set GPIO1.4 as GPIO (PHY \RST) + gpio_write(PIN('1', 4), 0); // reset PHY + + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08, + 4); // set for ENET_REF_CLK1 + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08] |= + IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_ENET_RMII_SELECT_INPUT, + 1); // drive peripheral from B0_08, so RMII clock is taken + // from ENET_REF_CLK1 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_HIGH, GPIO_PULL_UP); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09, 0); // set for RXDATA1 + periph_mux_config(kIOMUXC_ENET_RX_DATA1_SELECT_INPUT, + 1); // drive peripheral from B0_09 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_HIGH, GPIO_PULL_UP); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10, 0); // set for RXDATA0 + periph_mux_config(kIOMUXC_ENET_RX_DATA0_SELECT_INPUT, + 1); // drive peripheral from B0_10 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_HIGH, GPIO_PULL_UP); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11, 0); // set for CRS + periph_mux_config(kIOMUXC_ENET_RX_EN_SELECT_INPUT, + 1); // drive peripheral from B0_11 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_HIGH, GPIO_PULL_UP); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12, 0); // set for RXERR + periph_mux_config(kIOMUXC_ENET_RX_ERR_SELECT_INPUT, + 1); // drive peripheral from B0_12 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_HIGH, GPIO_PULL_UP); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13, 0); // set for TXEN + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_HIGH, GPIO_PULL_UP); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14, 0); // set for TXDATA0 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_HIGH, GPIO_PULL_UP); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15, 0); // set for TXDATA1 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_HIGH, GPIO_PULL_UP); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, 4); // set for MDIO + periph_mux_config(kIOMUXC_ENET_MDIO_SELECT_INPUT, + 2); // drive peripheral from EMC_40 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_MEDIUM, GPIO_PULL_UP); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, 4); // set for MDC + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_MEDIUM, GPIO_PULL_UP); + + gpio_init(PIN('1', 22), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, + GPIO_SPEED_MEDIUM, + GPIO_PULL_UP); // set GPIO1.22 as GPIO (PHY INTRP/NAND_TREE) + gpio_write(PIN('1', 22), 1); // prevent NAND_TREE + // 14.8.9 Use 500MHz reference and generate 50MHz. This is done at sysinit.c, + // as we use this source to clock the core + spin(10000); // keep PHY RST low for a while + gpio_write(PIN('1', 4), 1); // deassert RST + gpio_init(PIN('1', 22), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM, + GPIO_PULL_UP); // setup IRQ (pulled-up)(not used) + + IOMUXC_GPR->GPR1 |= + IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR(1); // Set ENET_REF_CLK1 as output + clock_periph(1, CCM_CCGR1_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enet_ipg_clk + NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler +} + +// Helper macro for MAC generation, byte reads not allowed +#define GENERATE_LOCALLY_ADMINISTERED_MAC() \ + { \ + 2, OCOTP->CFG0 & 255, (OCOTP->CFG0 >> 10) & 255, \ + ((OCOTP->CFG0 >> 19) ^ (OCOTP->CFG1 >> 19)) & 255, \ + (OCOTP->CFG1 >> 10) & 255, OCOTP->CFG1 & 255 \ + } diff --git a/examples/nxp/rt1020-evk-make-freertos-builtin/link_ram.ld b/examples/nxp/rt1020-evk-make-freertos-builtin/link_ram.ld new file mode 100644 index 00000000..25be4fb5 --- /dev/null +++ b/examples/nxp/rt1020-evk-make-freertos-builtin/link_ram.ld @@ -0,0 +1,16 @@ +ENTRY(Reset_Handler); +MEMORY { + itcram(rx) : ORIGIN = 0x00000000, LENGTH = 64k + dtcram(rw) : ORIGIN = 0x20000000, LENGTH = 64k + ocram(rw) : ORIGIN = 0x20200000, LENGTH = 128k /* This is cached */ +} +__StackTop = ORIGIN(dtcram) + LENGTH(dtcram); + +SECTIONS { + .irq : { KEEP(*(.isr_vector)) } > itcram + .text : { *(.text* .text.*) *(.rodata*) ; } > itcram + .data : { __data_start__ = .; *(.data SORT(.data.*)) __data_end__ = .; } > dtcram AT > itcram + __etext = LOADADDR(.data); + .bss : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > dtcram + _end = .; +} diff --git a/examples/nxp/rt1020-evk-make-freertos-builtin/main.c b/examples/nxp/rt1020-evk-make-freertos-builtin/main.c new file mode 100644 index 00000000..f3f10c40 --- /dev/null +++ b/examples/nxp/rt1020-evk-make-freertos-builtin/main.c @@ -0,0 +1,96 @@ +// Copyright (c) 2023 Cesanta Software Limited +// All rights reserved + +#include "hal.h" +#include "mongoose.h" + +#define BLINK_PERIOD_MS 1000 // LED blinking period in millis + +void mg_random(void *buf, size_t len) { // Use on-board RNG + for (size_t n = 0; n < len; n += sizeof(uint32_t)) { + uint32_t r = rng_read(); + memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); + } +} + +static void timer_fn(void *arg) { + struct mg_tcpip_if *ifp = arg; // And show + const char *names[] = {"down", "up", "req", "ready"}; // network stats + MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u", + names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent, + ifp->ndrop, ifp->nerr)); +} + +static void fn(struct mg_connection *c, int ev, void *ev_data, void *fn_data) { + struct mg_tcpip_if *ifp = (struct mg_tcpip_if *) fn_data; + if (ev == MG_EV_HTTP_MSG) { + struct mg_http_message *hm = (struct mg_http_message *) ev_data; + if (mg_http_match_uri(hm, "/api/hello")) { // Request to /api/hello + mg_http_reply(c, 200, "", "{%m:%u,%m:%u,%m:%u,%m:%u,%m:%u}\n", + MG_ESC("eth"), ifp->state, MG_ESC("frames_received"), + ifp->nrecv, MG_ESC("frames_sent"), ifp->nsent, + MG_ESC("frames_dropped"), ifp->ndrop, + MG_ESC("interface_errors"), ifp->nerr); + } else if (mg_http_match_uri(hm, "/")) { // Index page + mg_http_reply( + c, 200, "", "%s", + "" + "

Welcome to Mongoose

" + "See /api/hello for REST example" + ""); + } else { // All other URIs + mg_http_reply(c, 404, "", "Not Found\n"); + } + } +} + +static void server(void *args) { + struct mg_mgr mgr; // Initialise Mongoose event manager + mg_mgr_init(&mgr); // and attach it to the interface + mg_log_set(MG_LL_DEBUG); // Set log level + + // Initialise Mongoose network stack + ethernet_init(); + struct mg_tcpip_driver_imxrt1020_data driver_data = {.mdc_cr = 24}; + struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(), + // Uncomment below for static configuration: + // .ip = mg_htonl(MG_U32(192, 168, 0, 223)), + // .mask = mg_htonl(MG_U32(255, 255, 255, 0)), + // .gw = mg_htonl(MG_U32(192, 168, 0, 1)), + .driver = &mg_tcpip_driver_imxrt1020, + .driver_data = &driver_data}; + mg_tcpip_init(&mgr, &mif); + mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif); + + MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac)); + while (mif.state != MG_TCPIP_STATE_READY) { + mg_mgr_poll(&mgr, 0); + } + + MG_INFO(("Initialising application...")); + mg_http_listen(&mgr, "http://0.0.0.0:80", fn, &mif); + + MG_INFO(("Starting event loop")); + for (;;) mg_mgr_poll(&mgr, 1); // Infinite event loop + (void) args; +} + +static void blinker(void *args) { + gpio_output(LED); // Setup blue LED + for (;;) { + gpio_toggle(LED); + vTaskDelay(pdMS_TO_TICKS(BLINK_PERIOD_MS)); + } + (void) args; +} + +int main(void) { + uart_init(UART_DEBUG, 115200); // Initialise UART + + // Start tasks. NOTE: stack sizes are in 32-bit words + xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL); + xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL); + + vTaskStartScheduler(); // This blocks + return 0; +} diff --git a/examples/nxp/rt1020-evk-make-freertos-builtin/mongoose.c b/examples/nxp/rt1020-evk-make-freertos-builtin/mongoose.c new file mode 120000 index 00000000..5e522bbc --- /dev/null +++ b/examples/nxp/rt1020-evk-make-freertos-builtin/mongoose.c @@ -0,0 +1 @@ +../../../mongoose.c \ No newline at end of file diff --git a/examples/nxp/rt1020-evk-make-freertos-builtin/mongoose.h b/examples/nxp/rt1020-evk-make-freertos-builtin/mongoose.h new file mode 120000 index 00000000..ee4ac823 --- /dev/null +++ b/examples/nxp/rt1020-evk-make-freertos-builtin/mongoose.h @@ -0,0 +1 @@ +../../../mongoose.h \ No newline at end of file diff --git a/examples/nxp/rt1020-evk-make-freertos-builtin/mongoose_custom.h b/examples/nxp/rt1020-evk-make-freertos-builtin/mongoose_custom.h new file mode 100644 index 00000000..801bd564 --- /dev/null +++ b/examples/nxp/rt1020-evk-make-freertos-builtin/mongoose_custom.h @@ -0,0 +1,12 @@ +#pragma once + +#include // we are not using lwIP + +// See https://mongoose.ws/documentation/#build-options +#define MG_ARCH MG_ARCH_FREERTOS +#define MG_ENABLE_TCPIP 1 +#define MG_ENABLE_DRIVER_IMXRT1020 1 +#define MG_IO_SIZE 256 +#define MG_ENABLE_CUSTOM_RANDOM 1 +#define MG_ENABLE_PACKED_FS 1 + diff --git a/examples/nxp/rt1020-evk-make-freertos-builtin/syscalls.c b/examples/nxp/rt1020-evk-make-freertos-builtin/syscalls.c new file mode 100644 index 00000000..be3210aa --- /dev/null +++ b/examples/nxp/rt1020-evk-make-freertos-builtin/syscalls.c @@ -0,0 +1,85 @@ +#include + +#include "hal.h" + +int _fstat(int fd, struct stat *st) { + if (fd < 0) return -1; + st->st_mode = S_IFCHR; + return 0; +} + +void *_sbrk(int incr) { + extern char _end; + static unsigned char *heap = NULL; + unsigned char *prev_heap; + if (heap == NULL) heap = (unsigned char *) &_end; + prev_heap = heap; + heap += incr; + return prev_heap; +} + +int _open(const char *path) { + (void) path; + return -1; +} + +int _close(int fd) { + (void) fd; + return -1; +} + +int _isatty(int fd) { + (void) fd; + return 1; +} + +int _lseek(int fd, int ptr, int dir) { + (void) fd, (void) ptr, (void) dir; + return 0; +} + +void _exit(int status) { + (void) status; + for (;;) asm volatile("BKPT #0"); +} + +void _kill(int pid, int sig) { + (void) pid, (void) sig; +} + +int _getpid(void) { + return -1; +} + +int _write(int fd, char *ptr, int len) { + (void) fd, (void) ptr, (void) len; + if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len); + return -1; +} + +int _read(int fd, char *ptr, int len) { + (void) fd, (void) ptr, (void) len; + return -1; +} + +int _link(const char *a, const char *b) { + (void) a, (void) b; + return -1; +} + +int _unlink(const char *a) { + (void) a; + return -1; +} + +int _stat(const char *path, struct stat *st) { + (void) path, (void) st; + return -1; +} + +int mkdir(const char *path, mode_t mode) { + (void) path, (void) mode; + return -1; +} + +void _init(void) {} diff --git a/examples/nxp/rt1020-evk-make-freertos-builtin/sysinit.c b/examples/nxp/rt1020-evk-make-freertos-builtin/sysinit.c new file mode 100644 index 00000000..d60a5254 --- /dev/null +++ b/examples/nxp/rt1020-evk-make-freertos-builtin/sysinit.c @@ -0,0 +1,106 @@ +// Copyright (c) 2023 Cesanta Software Limited +// All rights reserved +// +// This file contains essentials required by the CMSIS: +// uint32_t SystemCoreClock - holds the system core clock value +// SystemInit() - initialises the system, e.g. sets up clocks + +#include "hal.h" + +uint32_t SystemCoreClock = SYS_FREQUENCY; + +// - 14.4, Figure 14-2: clock tree +// - 14.7.4: ARM_PODF defaults to /1 +// - 14.7.5: AHB_PODF defaults to /1; PERIPH_CLK_SEL defaults to derive clock +// from pre_periph_clk_sel +// - 14.7.6: PRE_PERIPH_CLK_SEL defaults to derive clock from PLL2 PFD3. +// - (For 528MHz operation, we need to set it to derive clock from PLL2, but +// this chip max is 500 MHz). +// - 14.6.1.3.1 System PLL (PLL2); 13.3.2.2 PLLs; 14.6.1.4 Phase Fractional +// Dividers (PFD) +// - 14.8.2: PLL2 is powered off and bypassed to 24MHz +// - 14.8.11: PFD defaults to 18/16 but Figure 14-2 shows half the value +// ("divider") +// - For 500MHz operation, we need to set PRE_PERIPH_CLK_SEL to derive clock +// from divided PLL6 +// - 14.8.9: configure PLL6 to generate a 500MHz clock +// - Datasheet 4.1.3: System frequency/Bus frequency max 500/125MHz respectively +// (AHB/IPG) +// - MCUXpresso: IPG_CLK_ROOT <= 125MHz; PERCLK_CLK_ROOT <= 62.5MHz +// - Datasheet 4.8.4.1.1/2: the processor clock frequency must exceed twice the +// ENET_RX_CLK/ENET_TX_CLK frequency. +// - Datasheet 4.8.4.2: no details for RMII (above is for MII), assumed 50MHz +// min processor clock +// - Datasheet 4.1.3, Table 11: "Overdrive" run mode requires 1.25V core voltage +// minimum +void SystemInit(void) { // Called automatically by startup code (ints masked) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU + asm("DSB"); + asm("ISB"); + // 53.4.2: Disable watchdog after reset (unlocked) + RTWDOG->CS &= ~RTWDOG_CS_EN_MASK; + RTWDOG->TOVAL = 0xFFFF; + while (RTWDOG->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock + while ((RTWDOG->CS & RTWDOG_CS_RCS_MASK) == 0) + spin(1); // wait for new config + // Set VDD_SOC to 1.25V + SETBITS(DCDC->REG3, DCDC_REG3_TRG_MASK, DCDC_REG3_TRG(0x12)); + while ((DCDC->REG0 & DCDC_REG0_STS_DC_OK_MASK) == 0) + spin(1); // Wait for DCDC_STS_DC_OK + // 14.8.9 Init 500MHz reference, clock the M7 core with it, generate 50MHz for + // ENET and RMII. + SETBITS(CCM_ANALOG->PLL_ENET, CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK, + CCM_ANALOG_PLL_ENET_BYPASS_MASK | + CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(0)); // bypass to 24MHz osc + SETBITS( + CCM_ANALOG->PLL_ENET, + CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK, + CCM_ANALOG_PLL_ENET_DIV_SELECT(1) | CCM_ANALOG_PLL_ENET_ENABLE_MASK | + CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK); // setup PLL + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) + spin(1); // wait until it is stable + CCM_ANALOG->PLL_ENET &= + ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; // Disable Bypass (switch to PLL) + SETBITS(CCM->CBCDR, CCM_CBCDR_IPG_PODF_MASK, + CCM_CBCDR_IPG_PODF(3)); // Set IPG divider /4 (125MHz) + SETBITS(CCM->CSCMR1, CCM_CSCMR1_PERCLK_PODF_MASK, + CCM_CSCMR1_PERCLK_PODF(1)); // Set PERCLK divider /2 (62.5MHz) + SETBITS(CCM->CBCMR, CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, + CCM_CBCMR_PRE_PERIPH_CLK_SEL(3)); // run from 500MHz clock + // 14.5 Table 14-4: uart_clk_root + // 14.4: uart_clk_root = PLL3/6 or OSC; CCM_CSCDR1 (14.7.9) defaults to + // PLL3/6/1 + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_POWER_MASK; // Power PLL on + while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) + spin(1); // wait until it is stable + CCM_ANALOG->PLL_USB1 &= + ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; // Disable Bypass (switch to PLL) + rng_init(); // Initialise random number generator + // NXP startup code calls SystemInit BEFORE initializing RAM... + SysTick_Config(SYS_FREQUENCY / 1000); // Sys tick every 1ms +} + +#if 0 +__attribute__((section(".cfg"), used)) uint32_t __cfg[] = {0x1234abcd}; + +extern uint32_t __isr_vector[]; +extern uint32_t __ivt_boot_data[]; + +__attribute__((section(".ivt"), used)) uint32_t __ivt[8] = { + 0x412000d1, // header: 41 - version, 2000 size, d1 tag + (uint32_t) __isr_vector, // entry + 0, // reserved + 0, // dcd + (uint32_t) __ivt_boot_data, // boot data + (uint32_t) __ivt, // this is us - ivt absolute address + 0, // csf absolute address + 0, // reserved for HAB +}; + +__attribute__((section(".ivt"), used)) uint32_t __ivt_boot_data[] = { + 0, // boot start location + 64 * 1024, // size + 0, // Plugin flag + 0Xffffffff // empty - extra data word +}; +#endif