mirror of
https://github.com/cesanta/mongoose.git
synced 2024-11-23 18:49:01 +08:00
move to Wizard
This commit is contained in:
Sergio R. Caprile
parent
949966964f
commit
b7b8b9219d
@ -1,58 +1,29 @@
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CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
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CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
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CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
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CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_h5/Include
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CFLAGS += -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard $(CFLAGS_EXTRA)
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LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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SOURCES = main.c syscalls.c sysinit.c
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SOURCES += cmsis_h5/Source/Templates/gcc/startup_stm32h573xx.s # ST startup file. Compiler-dependent!
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# Mongoose options are defined in mongoose_config.h
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SOURCES += mongoose.c net.c packed_fs.c
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# Example specific build options. See README.md
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CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\"
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ifeq ($(OS),Windows_NT)
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RM = cmd /C del /Q /F /S
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else
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RM = rm -rf
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endif
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BOARD = h573
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IDE = GCC+make
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RTOS = baremetal
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WIZARD_URL ?= http://mongoose.ws/wizard
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all build example: firmware.bin
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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firmware.bin: wizard
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make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
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firmware.elf: cmsis_core cmsis_h5 $(SOURCES) hal.h link.ld Makefile
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
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wizard:
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hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
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&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
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unzip wizard.zip
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cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h
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flash: firmware.bin
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st-flash --reset write $< 0x8000000
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cmsis_core: # ARM CMSIS core headers
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git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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cmsis_h5: # ST CMSIS headers for STM32H5 series
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git clone --depth 1 -b main https://github.com/STMicroelectronics/cmsis_device_h5 $@
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mbedtls: # mbedTLS library
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git clone --depth 1 -b v2.28.2 https://github.com/mbed-tls/mbedtls $@
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ifeq ($(TLS), mbedtls)
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CFLAGS += -DMG_TLS=MG_TLS_MBED -Wno-conversion -Imbedtls/include
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CFLAGS += -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" mbedtls/library/*.c
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firmware.elf: mbedtls
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endif
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# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
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#DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/
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DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/??
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update: firmware.bin
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
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test update: CFLAGS += -DUART_DEBUG=USART1
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test update: CFLAGS_EXTRA ="-DUART_DEBUG=USART?"
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test: update
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt
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grep 'READY, IP:' /tmp/output.txt # Check for network init
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clean:
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$(RM) firmware.* *.su cmsis_core cmsis_h5 mbedtls
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rm -rf firmware.* wizard*
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@ -1,3 +1 @@
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# Baremetal web device dashboard on STMH573I-DK
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See https://mongoose.ws/tutorials/stm32/all-make-baremetal-builtin/
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See [Wizard](https://mongoose.ws/wizard/#/output?board=h573&ide=GCC+make&rtos=baremetal&file=README.md)
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@ -1,175 +0,0 @@
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// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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//
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// Datasheet: RM0481, devboard manual: UM3143
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// https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf
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// Alternate functions: https://www.st.com/resource/en/datasheet/stm32h573ii.pdf
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#pragma once
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#include <stm32h573xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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#define LED1 PIN('I', 9) // On-board LED pin (green)
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#define LED2 PIN('I', 8) // On-board LED pin (orange)
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#define LED3 PIN('F', 1) // On-board LED pin (red)
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#define LED LED2 // Use orange LED for blinking
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#ifndef UART_DEBUG
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#define UART_DEBUG USART1
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#endif
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// System clock (11.4, Figure 48; 11.4.5, Figure 51; 11.4.8
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// CPU_FREQUENCY <= 250 MHz; (SYS_FREQUENCY / HPRE) ; hclk = CPU_FREQUENCY
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// APB clocks <= 250 MHz. Configure flash latency (WS) in accordance to hclk
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// freq (7.3.4, Table 37)
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enum {
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HPRE = 7, // register value, divisor value = BIT(value - 7) = / 1
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PPRE1 = 4, // register values, divisor value = BIT(value - 3) = / 2
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PPRE2 = 4,
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PPRE3 = 4,
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};
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// Make sure your chip package uses the internal LDO, otherwise set PLL1_N = 200
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enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 250, PLL1_P = 2 };
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#define CPU_FREQUENCY \
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((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / (BIT(HPRE - 7))) * 1000000)
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#define AHB_FREQUENCY CPU_FREQUENCY
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#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(PPRE2 - 3)))
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#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(PPRE1 - 3)))
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static inline void spin(volatile uint32_t n) {
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while (n--) (void) 0;
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}
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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#define GPIO(N) ((GPIO_TypeDef *) ((GPIOA_BASE_NS) + 0x400 * (N)))
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static GPIO_TypeDef *gpio_bank(uint16_t pin) {
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return GPIO(PINBANK(pin));
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}
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static inline void gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int gpio_read(uint16_t pin) {
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return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->AHB2ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
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SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline bool uart_init(USART_TypeDef *uart, unsigned long baud) {
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uint8_t af = 7; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
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if (uart == USART1) {
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freq = APB2_FREQUENCY, RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
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tx = PIN('A', 9), rx = PIN('A', 10);
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} else if (uart == USART2) {
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freq = APB1_FREQUENCY, RCC->APB1LENR |= RCC_APB1LENR_USART2EN;
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tx = PIN('A', 2), rx = PIN('A', 3);
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} else if (uart == USART3) {
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freq = APB1_FREQUENCY, RCC->APB1LENR |= RCC_APB1LENR_USART3EN;
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tx = PIN('D', 8), rx = PIN('D', 9);
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} else {
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return false;
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}
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gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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uart->CR1 = 0; // Disable UART
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uart->BRR = freq / baud; // Set baud rate
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uart->CR1 = USART_CR1_RE | USART_CR1_TE; // Set mode to TX & RX
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uart->CR1 |= USART_CR1_UE; // Enable UART
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return true;
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}
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static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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uart->TDR = byte;
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while ((uart->ISR & BIT(7)) == 0) spin(1);
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}
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static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(USART_TypeDef *uart) {
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return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->RDR & 255);
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}
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static inline void rng_init(void) {
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RCC->CCIPR5 |= RCC_CCIPR5_RNGSEL_0; // RNG clock source pll1_q_ck
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RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG clock
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RNG->CR |= RNG_CR_RNGEN; // Enable RNG
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}
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static inline uint32_t rng_read(void) {
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while ((RNG->SR & RNG_SR_DRDY) == 0) spin(1);
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return RNG->DR;
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}
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static inline bool ldo_is_on(void) {
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return (PWR->SCCR & PWR_SCCR_LDOEN) == PWR_SCCR_LDOEN;
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}
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// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
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static inline void ethernet_init(void) {
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// Initialise Ethernet. Enable MAC GPIO pins, see UM3115 section 10.7
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uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),
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PIN('C', 1), PIN('C', 4), PIN('C', 5),
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PIN('G', 11), PIN('G', 12), PIN('G', 13)};
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for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
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gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
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GPIO_PULL_NONE, 11); // 11 is the Ethernet function
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}
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NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
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RCC->APB3ENR |= RCC_APB3ENR_SBSEN; // Enable SBS clock
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SETBITS(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY, SBS_PMCR_ETH_SEL_PHY_2); // RMII
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RCC->AHB1ENR |= RCC_AHB1ENR_ETHEN | RCC_AHB1ENR_ETHRXEN | RCC_AHB1ENR_ETHTXEN;
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}
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#define UUID ((uint32_t *) UID_BASE) // Unique 96-bit chip ID. TRM 59.1
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// Helper macro for MAC generation, byte reads not allowed
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ \
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2, UUID[0] & 255, (UUID[0] >> 10) & 255, (UUID[0] >> 19) & 255, \
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UUID[1] & 255, UUID[2] & 255 \
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}
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@ -1,30 +0,0 @@
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ENTRY(Reset_Handler);
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MEMORY {
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flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
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sram(rwx) : ORIGIN = 0x20000000, LENGTH = 640k
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}
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_estack = ORIGIN(sram) + LENGTH(sram); /* End of RAM. stack points here */
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SECTIONS {
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.vectors : { KEEP(*(.isr_vector)) } > flash
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.text : { *(.text* .text.*) } > flash
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.rodata : { *(.rodata*) } > flash
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.data : {
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_sdata = .;
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*(.first_data)
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*(.ram)
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*(.data SORT(.data.*))
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_edata = .;
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} > sram AT > flash
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_sidata = LOADADDR(.data);
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.bss : {
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_sbss = .;
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*(.bss SORT(.bss.*) COMMON)
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_ebss = .;
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} > sram
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. = ALIGN(8);
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_end = .;
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}
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@ -1,89 +0,0 @@
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// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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#include "hal.h"
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#include "mongoose.h"
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#include "net.h"
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#define BLINK_PERIOD_MS 1000 // LED blinking period in millis
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static volatile uint64_t s_ticks; // Milliseconds since boot
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void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
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s_ticks++;
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}
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uint64_t mg_millis(void) { // Let Mongoose use our uptime function
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return s_ticks; // Return number of milliseconds since boot
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}
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bool mg_random(void *buf, size_t len) { // Use on-board RNG
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for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
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uint32_t r = rng_read();
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memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
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||||
}
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return true;
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||||
}
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||||
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static void timer_fn(void *arg) {
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gpio_toggle(LED); // Blink LED
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struct mg_tcpip_if *ifp = arg; // And show
|
||||
const char *names[] = {"down", "up", "req", "ready"}; // network stats
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||||
MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
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names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
|
||||
ifp->ndrop, ifp->nerr));
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||||
}
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||||
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||||
int main(void) {
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||||
gpio_output(LED); // Setup green LED
|
||||
uart_init(UART_DEBUG, 115200); // Initialise debug printf
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||||
ethernet_init(); // Initialise ethernet pins
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||||
MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000));
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||||
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||||
struct mg_mgr mgr; // Initialise
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||||
mg_mgr_init(&mgr); // Mongoose event manager
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||||
mg_log_set(MG_LL_DEBUG); // Set log level
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mg_ota_boot(); // Call bootloader: continue to load, or boot another FW
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||||
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#if MG_OTA == MG_OTA_FLASH
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// Demonstrate the use of mg_flash_{load/save} functions for storing device
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// configuration data on flash. Increment boot count on every boot.
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struct deviceconfig {
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uint32_t boot_count;
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char some_other_data[40];
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};
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uint32_t key = 0x12345678; // A unique key, one per data type
|
||||
struct deviceconfig dc = {}; // Initialise to some default values
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||||
mg_flash_load(NULL, key, &dc, sizeof(dc)); // Load from flash
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||||
dc.boot_count++; // Increment boot count
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||||
mg_flash_save(NULL, key, &dc, sizeof(dc)); // And save back
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||||
MG_INFO(("Boot count: %u", dc.boot_count)); // Print boot count
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||||
#endif
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||||
// Initialise Mongoose network stack
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||||
struct mg_tcpip_driver_stm32h_data driver_data = {.mdc_cr = 4};
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struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
|
||||
// Uncomment below for static configuration:
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||||
// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
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||||
// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
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||||
// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
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||||
.driver = &mg_tcpip_driver_stm32h,
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||||
.driver_data = &driver_data};
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||||
mg_tcpip_init(&mgr, &mif);
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||||
mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
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||||
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||||
MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
|
||||
while (mif.state != MG_TCPIP_STATE_READY) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
MG_INFO(("Initialising application..."));
|
||||
web_init(&mgr);
|
||||
|
||||
MG_INFO(("Starting event loop"));
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.c
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.h
|
||||
@ -1,13 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_NEWLIB
|
||||
#define MG_OTA MG_OTA_FLASH
|
||||
#define MG_DEVICE MG_DEVICE_STM32H5
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
#define MG_ENABLE_DRIVER_STM32H 1
|
||||
#define MG_ENABLE_LINES 1
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.c
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.h
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/packed_fs.c
|
||||
@ -1,98 +0,0 @@
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
int _fstat(int fd, struct stat *st) {
|
||||
if (fd < 0) return -1;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
extern char _end;
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
unsigned char x = 0, *heap_end = (unsigned char *)((size_t) &x - 512);
|
||||
(void) x;
|
||||
if (heap == NULL) heap = (unsigned char *) &_end;
|
||||
prev_heap = heap;
|
||||
if (heap + incr > heap_end) return (void *) -1;
|
||||
heap += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int mkdir(const char *path, mode_t mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {}
|
||||
|
||||
extern uint64_t mg_now(void);
|
||||
|
||||
int _gettimeofday(struct timeval *tv, void *tz) {
|
||||
uint64_t now = mg_now();
|
||||
(void) tz;
|
||||
tv->tv_sec = (time_t) (now / 1000);
|
||||
tv->tv_usec = (unsigned long) ((now % 1000) * 1000);
|
||||
return 0;
|
||||
}
|
||||
@ -1,45 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// This file contains essentials required by the CMSIS:
|
||||
// uint32_t SystemCoreClock - holds the system core clock value
|
||||
// SystemInit() - initialises the system, e.g. sets up clocks
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
uint32_t SystemCoreClock = CPU_FREQUENCY;
|
||||
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
SCB->CPACR |= ((3UL << 20U) | (3UL << 22U)); // Enable FPU
|
||||
asm("DSB");
|
||||
asm("ISB");
|
||||
|
||||
// Set flash latency. RM0481, section 7.11.1, section 7.3.4 table 37
|
||||
SETBITS(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
|
||||
FLASH_ACR_LATENCY_5WS | FLASH_ACR_WRHIGHFREQ_1);
|
||||
|
||||
if (ldo_is_on()) {
|
||||
PWR->VOSCR = PWR_VOSCR_VOS_0 | PWR_VOSCR_VOS_1; // Select VOS0
|
||||
} else {
|
||||
PWR->VOSCR = PWR_VOSCR_VOS_1; // Select VOS1
|
||||
}
|
||||
uint32_t f = PWR->VOSCR; // fake read to wait for bus clocking
|
||||
while ((PWR->VOSSR & PWR_VOSSR_ACTVOSRDY) == 0) spin(1);
|
||||
(void) f;
|
||||
RCC->CR = RCC_CR_HSION; // Clear HSI clock divisor
|
||||
while ((RCC->CR & RCC_CR_HSIRDY) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR2 = (PPRE3 << 12) | (PPRE2 << 8) | (PPRE1 << 4) | (HPRE << 0);
|
||||
RCC->PLL1DIVR =
|
||||
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0); // Set PLL1_P PLL1_N
|
||||
// Enable P and Q divider outputs; set PLL1_M, select HSI as source,
|
||||
// !PLL1VCOSEL, PLL1RGE=0
|
||||
RCC->PLL1CFGR =
|
||||
RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1PEN | (PLL1_M << 8) | (1 << 0);
|
||||
RCC->CR |= RCC_CR_PLL1ON; // Enable PLL1
|
||||
while ((RCC->CR & RCC_CR_PLL1RDY) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR1 |= (3 << 0); // Set clock source to PLL1
|
||||
while ((RCC->CFGR1 & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
|
||||
|
||||
rng_init(); // Initialise random number generator
|
||||
SysTick_Config(CPU_FREQUENCY / 1000); // Sys tick every 1ms
|
||||
}
|
||||
@ -1,44 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configCPU_CLOCK_HZ CPU_FREQUENCY
|
||||
#define configTICK_RATE_HZ 1000
|
||||
#define configMAX_PRIORITIES 5
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TIMERS 0
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configUSE_MALLOC_FAILED_HOOK 0
|
||||
#define configMINIMAL_STACK_SIZE 128
|
||||
#define configTOTAL_HEAP_SIZE (1024 * 128)
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_xTaskGetSchedulerState 1 // trying
|
||||
|
||||
#ifdef __NVIC_PRIO_BITS
|
||||
#define configPRIO_BITS __NVIC_PRIO_BITS
|
||||
#else
|
||||
#define configPRIO_BITS 4
|
||||
#endif
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
|
||||
#define configKERNEL_INTERRUPT_PRIORITY \
|
||||
(configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
|
||||
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
|
||||
(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
|
||||
|
||||
#define configASSERT(expr) \
|
||||
if (!(expr)) printf("FAILURE %s:%d: %s\n", __FILE__, __LINE__, #expr)
|
||||
|
||||
// https://www.freertos.org/2020/04/using-freertos-on-armv8-m-microcontrollers.html
|
||||
#define configENABLE_FPU 1
|
||||
#define configENABLE_MPU 0
|
||||
#define configENABLE_TRUSTZONE 0
|
||||
#define configRUN_FREERTOS_SECURE_ONLY 0
|
||||
|
||||
//#define vPortSVCHandler SVC_Handler
|
||||
//#define xPortPendSVHandler PendSV_Handler
|
||||
//#define xPortSysTickHandler SysTick_Handler
|
||||
@ -1,59 +1,29 @@
|
||||
CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
|
||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
|
||||
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_h5/Include
|
||||
CFLAGS += -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard $(CFLAGS_EXTRA)
|
||||
LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
|
||||
|
||||
SOURCES = main.c syscalls.c sysinit.c
|
||||
SOURCES += cmsis_h5/Source/Templates/gcc/startup_stm32h573xx.s # ST startup file. Compiler-dependent!
|
||||
|
||||
# FreeRTOS. H5 has a Cortex-M33 (ARMv8) core, the CM4F port can be used if TrustZone and the MPU are not to be used, see H7 example
|
||||
SOURCES += FreeRTOS-Kernel/portable/MemMang/heap_4.c
|
||||
SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
|
||||
SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
|
||||
CFLAGS += -IFreeRTOS-Kernel/include
|
||||
CFLAGS += -IFreeRTOS-Kernel/portable/GCC/ARM_CM33_NTZ/non_secure -Wno-conversion -Wno-unused-parameter
|
||||
|
||||
# Mongoose options are defined in mongoose_config.h
|
||||
SOURCES += mongoose.c net.c packed_fs.c
|
||||
|
||||
# Example specific build options. See README.md
|
||||
CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\"
|
||||
|
||||
ifeq ($(OS),Windows_NT)
|
||||
RM = cmd /C del /Q /F /S
|
||||
else
|
||||
RM = rm -rf
|
||||
endif
|
||||
BOARD = h573
|
||||
IDE = GCC+make
|
||||
RTOS = FreeRTOS
|
||||
WIZARD_URL ?= http://mongoose.ws/wizard
|
||||
|
||||
all build example: firmware.bin
|
||||
|
||||
firmware.bin: firmware.elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
firmware.bin: wizard
|
||||
make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
|
||||
|
||||
firmware.elf: FreeRTOS-Kernel cmsis_core cmsis_h5 $(SOURCES) hal.h link.ld mongoose_config.h FreeRTOSConfig.h Makefile
|
||||
arm-none-eabi-gcc $(SOURCES) $(wildcard FreeRTOS-Kernel/*.c) $(CFLAGS) $(LDFLAGS) -o $@
|
||||
wizard:
|
||||
hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
|
||||
&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
|
||||
unzip wizard.zip
|
||||
cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h
|
||||
|
||||
flash: firmware.bin
|
||||
st-flash --debug --freq=200 --reset write $< 0x8000000
|
||||
|
||||
cmsis_core: # ARM CMSIS core headers
|
||||
git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
|
||||
cmsis_h5: # ST CMSIS headers for STM32H5 series
|
||||
git clone --depth 1 -b main https://github.com/STMicroelectronics/cmsis_device_h5 $@
|
||||
FreeRTOS-Kernel: # FreeRTOS sources
|
||||
git clone --depth 1 -b V10.5.0 https://github.com/FreeRTOS/FreeRTOS-Kernel $@
|
||||
|
||||
# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
|
||||
#DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/
|
||||
DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/??
|
||||
update: firmware.bin
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
|
||||
|
||||
test update: CFLAGS += -DUART_DEBUG=USART1
|
||||
test update: CFLAGS_EXTRA ="-DUART_DEBUG=USART?"
|
||||
test: update
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt
|
||||
grep 'READY, IP:' /tmp/output.txt # Check for network init
|
||||
|
||||
clean:
|
||||
$(RM) firmware.* *.su cmsis_core cmsis_h5 FreeRTOS-Kernel
|
||||
rm -rf firmware.* wizard*
|
||||
|
||||
@ -1,3 +1 @@
|
||||
# FreeRTOS web device dashboard on STMH573I-DK
|
||||
|
||||
See https://mongoose.ws/tutorials/stm32/all-make-freertos-builtin/
|
||||
See [Wizard](https://mongoose.ws/wizard/#/output?board=h573&ide=GCC+make&rtos=FreeRTOS&file=README.md)
|
||||
|
||||
@ -1,175 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// Datasheet: RM0481, devboard manual: UM3143
|
||||
// https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf
|
||||
// Alternate functions: https://www.st.com/resource/en/datasheet/stm32h573ii.pdf
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stm32h573xx.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
|
||||
#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
#define LED1 PIN('I', 9) // On-board LED pin (green)
|
||||
#define LED2 PIN('I', 8) // On-board LED pin (orange)
|
||||
#define LED3 PIN('F', 1) // On-board LED pin (red)
|
||||
|
||||
#define LED LED2 // Use orange LED for blinking
|
||||
|
||||
// System clock (11.4, Figure 48; 11.4.5, Figure 51; 11.4.8
|
||||
// CPU_FREQUENCY <= 250 MHz; (SYS_FREQUENCY / HPRE) ; hclk = CPU_FREQUENCY
|
||||
// APB clocks <= 250 MHz. Configure flash latency (WS) in accordance to hclk
|
||||
// freq (7.3.4, Table 37)
|
||||
enum {
|
||||
HPRE = 7, // register value, divisor value = BIT(value - 7) = / 1
|
||||
PPRE1 = 4, // register values, divisor value = BIT(value - 3) = / 2
|
||||
PPRE2 = 4,
|
||||
PPRE3 = 4,
|
||||
};
|
||||
// Make sure your chip package uses the internal LDO, otherwise set PLL1_N = 200
|
||||
enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 250, PLL1_P = 2 };
|
||||
#define CPU_FREQUENCY \
|
||||
((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / (BIT(HPRE - 7))) * 1000000)
|
||||
#define AHB_FREQUENCY CPU_FREQUENCY
|
||||
#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(PPRE2 - 3)))
|
||||
#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(PPRE1 - 3)))
|
||||
|
||||
static inline void spin(volatile uint32_t n) {
|
||||
while (n--) (void) 0;
|
||||
}
|
||||
|
||||
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
|
||||
enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
|
||||
enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
|
||||
|
||||
#define GPIO(N) ((GPIO_TypeDef *) ((GPIOA_BASE_NS) + 0x400 * (N)))
|
||||
|
||||
static GPIO_TypeDef *gpio_bank(uint16_t pin) {
|
||||
return GPIO(PINBANK(pin));
|
||||
}
|
||||
static inline void gpio_toggle(uint16_t pin) {
|
||||
GPIO_TypeDef *gpio = gpio_bank(pin);
|
||||
uint32_t mask = BIT(PINNO(pin));
|
||||
gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
|
||||
}
|
||||
static inline int gpio_read(uint16_t pin) {
|
||||
return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
|
||||
}
|
||||
static inline void gpio_write(uint16_t pin, bool val) {
|
||||
GPIO_TypeDef *gpio = gpio_bank(pin);
|
||||
gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
|
||||
}
|
||||
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull, uint8_t af) {
|
||||
GPIO_TypeDef *gpio = gpio_bank(pin);
|
||||
uint8_t n = (uint8_t) (PINNO(pin));
|
||||
RCC->AHB2ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
|
||||
SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
|
||||
SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
|
||||
SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
|
||||
SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
|
||||
((uint32_t) af) << ((n & 7) * 4));
|
||||
SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
|
||||
}
|
||||
static inline void gpio_input(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 0);
|
||||
}
|
||||
static inline void gpio_output(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 0);
|
||||
}
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG USART3
|
||||
#endif
|
||||
|
||||
static inline bool uart_init(USART_TypeDef *uart, unsigned long baud) {
|
||||
uint8_t af = 7; // Alternate function
|
||||
uint16_t rx = 0, tx = 0; // pins
|
||||
uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
|
||||
|
||||
if (uart == USART1) {
|
||||
freq = APB2_FREQUENCY, RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
|
||||
tx = PIN('A', 9), rx = PIN('A', 10);
|
||||
} else if (uart == USART2) {
|
||||
freq = APB1_FREQUENCY, RCC->APB1LENR |= RCC_APB1LENR_USART2EN;
|
||||
tx = PIN('A', 2), rx = PIN('A', 3);
|
||||
} else if (uart == USART3) {
|
||||
freq = APB1_FREQUENCY, RCC->APB1LENR |= RCC_APB1LENR_USART3EN;
|
||||
tx = PIN('D', 8), rx = PIN('D', 9);
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
|
||||
gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
|
||||
uart->CR1 = 0; // Disable UART
|
||||
uart->BRR = freq / baud; // Set baud rate
|
||||
uart->CR1 = USART_CR1_RE | USART_CR1_TE; // Set mode to TX & RX
|
||||
uart->CR1 |= USART_CR1_UE; // Enable UART
|
||||
return true;
|
||||
}
|
||||
static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
|
||||
uart->TDR = byte;
|
||||
while ((uart->ISR & BIT(7)) == 0) spin(1);
|
||||
}
|
||||
static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int uart_read_ready(USART_TypeDef *uart) {
|
||||
return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
|
||||
}
|
||||
static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
|
||||
return (uint8_t) (uart->RDR & 255);
|
||||
}
|
||||
|
||||
static inline void rng_init(void) {
|
||||
RCC->CCIPR5 |= RCC_CCIPR5_RNGSEL_0; // RNG clock source pll1_q_ck
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG clock
|
||||
RNG->CR |= RNG_CR_RNGEN; // Enable RNG
|
||||
}
|
||||
static inline uint32_t rng_read(void) {
|
||||
while ((RNG->SR & RNG_SR_DRDY) == 0) spin(1);
|
||||
return RNG->DR;
|
||||
}
|
||||
|
||||
static inline bool ldo_is_on(void) {
|
||||
return (PWR->SCCR & PWR_SCCR_LDOEN) == PWR_SCCR_LDOEN;
|
||||
}
|
||||
|
||||
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
|
||||
static inline void ethernet_init(void) {
|
||||
// Initialise Ethernet. Enable MAC GPIO pins, see UM3115 section 10.7
|
||||
uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),
|
||||
PIN('C', 1), PIN('C', 4), PIN('C', 5),
|
||||
PIN('G', 11), PIN('G', 12), PIN('G', 13)};
|
||||
for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
|
||||
gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
|
||||
GPIO_PULL_NONE, 11); // 11 is the Ethernet function
|
||||
}
|
||||
NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
|
||||
RCC->APB3ENR |= RCC_APB3ENR_SBSEN; // Enable SBS clock
|
||||
SETBITS(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY, SBS_PMCR_ETH_SEL_PHY_2); // RMII
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_ETHEN | RCC_AHB1ENR_ETHRXEN | RCC_AHB1ENR_ETHTXEN;
|
||||
}
|
||||
|
||||
#define UUID ((uint32_t *) UID_BASE) // Unique 96-bit chip ID. TRM 59.1
|
||||
|
||||
// Helper macro for MAC generation, byte reads not allowed
|
||||
#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
|
||||
{ \
|
||||
2, UUID[0] & 255, (UUID[0] >> 10) & 255, (UUID[0] >> 19) & 255, \
|
||||
UUID[1] & 255, UUID[2] & 255 \
|
||||
}
|
||||
@ -1,29 +0,0 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
|
||||
sram(rwx) : ORIGIN = 0x20000000, LENGTH = 640k
|
||||
}
|
||||
_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
|
||||
|
||||
SECTIONS {
|
||||
.vectors : { KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text* .text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.data : {
|
||||
_sdata = .; /* for init_ram() */
|
||||
*(.first_data)
|
||||
*(.data SORT(.data.*))
|
||||
_edata = .; /* for init_ram() */
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : {
|
||||
_sbss = .; /* for init_ram() */
|
||||
*(.bss SORT(.bss.*) COMMON)
|
||||
_ebss = .; /* for init_ram() */
|
||||
} > sram
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .; /* for cmsis_gcc.h and init_ram() */
|
||||
}
|
||||
@ -1,76 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
#include "net.h"
|
||||
|
||||
#define BLINK_PERIOD_MS 1000 // LED blinking period in millis
|
||||
|
||||
bool mg_random(void *buf, size_t len) { // Use on-board RNG
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void timer_fn(void *arg) {
|
||||
struct mg_tcpip_if *ifp = arg; // And show
|
||||
const char *names[] = {"down", "up", "req", "ready"}; // network stats
|
||||
MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
|
||||
names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
|
||||
ifp->ndrop, ifp->nerr));
|
||||
}
|
||||
|
||||
static void server(void *args) {
|
||||
struct mg_mgr mgr; // Initialise Mongoose event manager
|
||||
mg_mgr_init(&mgr); // and attach it to the interface
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level
|
||||
|
||||
// Initialise Mongoose network stack
|
||||
ethernet_init();
|
||||
struct mg_tcpip_driver_stm32h_data driver_data = {.mdc_cr = 4};
|
||||
struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
|
||||
// Uncomment below for static configuration:
|
||||
// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
|
||||
// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
|
||||
// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
|
||||
.driver = &mg_tcpip_driver_stm32h,
|
||||
.driver_data = &driver_data};
|
||||
mg_tcpip_init(&mgr, &mif);
|
||||
mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
|
||||
|
||||
MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
|
||||
while (mif.state != MG_TCPIP_STATE_READY) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
MG_INFO(("Initialising application..."));
|
||||
web_init(&mgr);
|
||||
|
||||
MG_INFO(("Starting event loop"));
|
||||
for (;;) mg_mgr_poll(&mgr, 1); // Infinite event loop
|
||||
(void) args;
|
||||
}
|
||||
|
||||
static void blinker(void *args) {
|
||||
gpio_init(LED, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_NONE, 0);
|
||||
for (;;) {
|
||||
gpio_toggle(LED);
|
||||
vTaskDelay(pdMS_TO_TICKS(BLINK_PERIOD_MS));
|
||||
}
|
||||
(void) args;
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
uart_init(UART_DEBUG, 115200); // Initialise UART
|
||||
|
||||
// Start tasks. NOTE: stack sizes are in 32-bit words
|
||||
xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL);
|
||||
xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL);
|
||||
|
||||
vTaskStartScheduler(); // This blocks
|
||||
return 0;
|
||||
}
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.c
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.h
|
||||
@ -1,13 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
#include <errno.h> // we are not using lwIP
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_FREERTOS
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_DRIVER_STM32H 1
|
||||
#define MG_IO_SIZE 256
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.c
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.h
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/packed_fs.c
|
||||
@ -1,85 +0,0 @@
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
int _fstat(int fd, struct stat *st) {
|
||||
if (fd < 0) return -1;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
extern char _end;
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
if (heap == NULL) heap = (unsigned char *) &_end;
|
||||
prev_heap = heap;
|
||||
heap += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int mkdir(const char *path, mode_t mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {}
|
||||
@ -1,45 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// This file contains essentials required by the CMSIS:
|
||||
// uint32_t SystemCoreClock - holds the system core clock value
|
||||
// SystemInit() - initialises the system, e.g. sets up clocks
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
uint32_t SystemCoreClock = CPU_FREQUENCY;
|
||||
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
SCB->CPACR |= ((3UL << 20U) | (3UL << 22U)); // Enable FPU
|
||||
asm("DSB");
|
||||
asm("ISB");
|
||||
|
||||
// Set flash latency. RM0481, section 7.11.1, section 7.3.4 table 37
|
||||
SETBITS(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
|
||||
FLASH_ACR_LATENCY_5WS | FLASH_ACR_WRHIGHFREQ_1);
|
||||
|
||||
if (ldo_is_on()) {
|
||||
PWR->VOSCR = PWR_VOSCR_VOS_0 | PWR_VOSCR_VOS_1; // Select VOS0
|
||||
} else {
|
||||
PWR->VOSCR = PWR_VOSCR_VOS_1; // Select VOS1
|
||||
}
|
||||
uint32_t f = PWR->VOSCR; // fake read to wait for bus clocking
|
||||
while ((PWR->VOSSR & PWR_VOSSR_ACTVOSRDY) == 0) spin(1);
|
||||
(void) f;
|
||||
RCC->CR = RCC_CR_HSION; // Clear HSI clock divisor
|
||||
while ((RCC->CR & RCC_CR_HSIRDY) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR2 = (PPRE3 << 12) | (PPRE2 << 8) | (PPRE1 << 4) | (HPRE << 0);
|
||||
RCC->PLL1DIVR =
|
||||
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0); // Set PLL1_P PLL1_N
|
||||
// Enable P and Q divider outputs; set PLL1_M, select HSI as source,
|
||||
// !PLL1VCOSEL, PLL1RGE=0
|
||||
RCC->PLL1CFGR =
|
||||
RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1PEN | (PLL1_M << 8) | (1 << 0);
|
||||
RCC->CR |= RCC_CR_PLL1ON; // Enable PLL1
|
||||
while ((RCC->CR & RCC_CR_PLL1RDY) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR1 |= (3 << 0); // Set clock source to PLL1
|
||||
while ((RCC->CFGR1 & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
|
||||
|
||||
rng_init(); // Initialise random number generator
|
||||
// let FreeRTOS initialize SysTick
|
||||
}
|
||||
@ -1,59 +1,29 @@
|
||||
CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
|
||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
|
||||
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_h7/Include -DCORE_CM7
|
||||
CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
|
||||
LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
|
||||
|
||||
SOURCES = main.c syscalls.c sysinit.c
|
||||
SOURCES += cmsis_h7/Source/Templates/gcc/startup_stm32h747xx.s # ST startup file. Compiler-dependent!
|
||||
|
||||
# Mongoose options are defined in mongoose_config.h
|
||||
SOURCES += mongoose.c net.c packed_fs.c
|
||||
|
||||
# Example specific build options. See README.md
|
||||
CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\"
|
||||
|
||||
ifeq ($(OS),Windows_NT)
|
||||
RM = cmd /C del /Q /F /S
|
||||
else
|
||||
RM = rm -rf
|
||||
endif
|
||||
BOARD = h747
|
||||
IDE = GCC+make
|
||||
RTOS = baremetal
|
||||
WIZARD_URL ?= http://mongoose.ws/wizard
|
||||
|
||||
all build example: firmware.bin
|
||||
|
||||
firmware.bin: firmware.elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
arm-none-eabi-size --format=berkeley $<
|
||||
firmware.bin: wizard
|
||||
make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
|
||||
|
||||
firmware.elf: cmsis_core cmsis_h7 $(SOURCES) hal.h link.ld Makefile
|
||||
arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
|
||||
wizard:
|
||||
hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
|
||||
&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
|
||||
unzip wizard.zip
|
||||
cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h
|
||||
|
||||
flash: firmware.bin
|
||||
st-flash --reset write $< 0x8000000
|
||||
|
||||
cmsis_core: # ARM CMSIS core headers
|
||||
git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
|
||||
cmsis_h7: # ST CMSIS headers for STM32H7 series
|
||||
git clone --depth 1 -b v1.10.3 https://github.com/STMicroelectronics/cmsis_device_h7 $@
|
||||
mbedtls: # mbedTLS library
|
||||
git clone --depth 1 -b v2.28.2 https://github.com/mbed-tls/mbedtls $@
|
||||
|
||||
ifeq ($(TLS), mbedtls)
|
||||
CFLAGS += -DMG_TLS=MG_TLS_MBED -Wno-conversion -Imbedtls/include
|
||||
CFLAGS += -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" mbedtls/library/*.c
|
||||
firmware.elf: mbedtls
|
||||
endif
|
||||
|
||||
# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
|
||||
DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/6
|
||||
DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/??
|
||||
update: firmware.bin
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
|
||||
|
||||
test update: CFLAGS += -DUART_DEBUG=USART1
|
||||
test update: CFLAGS_EXTRA ="-DUART_DEBUG=USART?"
|
||||
test: update
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt
|
||||
grep 'READY, IP:' /tmp/output.txt # Check for network init
|
||||
|
||||
clean:
|
||||
$(RM) firmware.* *.su cmsis_core cmsis_h7 mbedtls
|
||||
rm -rf firmware.* wizard*
|
||||
|
||||
@ -1,3 +1 @@
|
||||
# Baremetal web device dashboard on STM32H747I-DISCO
|
||||
|
||||
See https://mongoose.ws/tutorials/stm32/all-make-baremetal-builtin/
|
||||
See [Wizard](https://mongoose.ws/wizard/#/output?board=h747&ide=GCC+make&rtos=baremetal&file=README.md)
|
||||
|
||||
@ -1,186 +0,0 @@
|
||||
// Copyright (c) 2022-2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// RM0399
|
||||
// https://www.st.com/resource/en/reference_manual/rm0399-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
|
||||
// https://www.st.com/resource/en/datasheet/stm32h747xi.pdf
|
||||
|
||||
#pragma once
|
||||
|
||||
#define LED1 PIN('I', 12) // On-board LED pin (green)
|
||||
#define LED2 PIN('I', 13) // On-board LED pin (yellow)
|
||||
#define LED3 PIN('I', 14) // On-board LED pin (red)
|
||||
#define LED LED2 // Use yellow LED for blinking
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG USART1
|
||||
#endif
|
||||
|
||||
#include <stm32h747xx.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
|
||||
#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
// System clock (2.1, Figure 1; 8.5, Figure 45; 8.5.5, Figure 47; 8.5.6, Figure
|
||||
// 49) CPU_FREQUENCY <= 480 MHz; hclk = CPU_FREQUENCY / HPRE ; hclk <= 240 MHz;
|
||||
// APB clocks <= 120 MHz. D1 domain bus matrix (and so flash) runs at hclk
|
||||
// frequency. Configure flash latency (WS) in accordance to hclk freq (4.3.8,
|
||||
// Table 17) The Ethernet controller is in D2 domain and runs at hclk frequency
|
||||
enum {
|
||||
D1CPRE = 1, // actual divisor value
|
||||
HPRE = 2, // actual divisor value
|
||||
D1PPRE = 4, // register values, divisor value = BIT(value - 3) = / 2
|
||||
D2PPRE1 = 4,
|
||||
D2PPRE2 = 4,
|
||||
D3PPRE = 4
|
||||
};
|
||||
// PLL1_P: odd division factors are not allowed (8.7.13) (according to Cube, '1'
|
||||
// is also an "odd division factor").
|
||||
// Make sure your chip is revision 'V', otherwise set PLL1_N = 400
|
||||
enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 480, PLL1_P = 2 };
|
||||
#define FLASH_LATENCY 0x24 // WRHIGHFREQ LATENCY
|
||||
#define CPU_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / D1CPRE) * 1000000)
|
||||
//#define CPU_FREQUENCY ((PLL1_HSI / D1CPRE) * 1000000)
|
||||
//#define CPU_FREQUENCY 64000000
|
||||
#define AHB_FREQUENCY (CPU_FREQUENCY / HPRE)
|
||||
#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(D2PPRE2 - 3)))
|
||||
#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(D2PPRE1 - 3)))
|
||||
|
||||
static inline void spin(volatile uint32_t n) {
|
||||
while (n--) (void) 0;
|
||||
}
|
||||
|
||||
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
|
||||
enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
|
||||
enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
|
||||
|
||||
#define GPIO(N) ((GPIO_TypeDef *) (0x40000000 + 0x18020000UL + 0x400 * (N)))
|
||||
|
||||
static GPIO_TypeDef *gpio_bank(uint16_t pin) {
|
||||
return GPIO(PINBANK(pin));
|
||||
}
|
||||
static inline void gpio_toggle(uint16_t pin) {
|
||||
GPIO_TypeDef *gpio = gpio_bank(pin);
|
||||
uint32_t mask = BIT(PINNO(pin));
|
||||
gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
|
||||
}
|
||||
static inline int gpio_read(uint16_t pin) {
|
||||
return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
|
||||
}
|
||||
static inline void gpio_write(uint16_t pin, bool val) {
|
||||
GPIO_TypeDef *gpio = gpio_bank(pin);
|
||||
gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
|
||||
}
|
||||
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull, uint8_t af) {
|
||||
GPIO_TypeDef *gpio = gpio_bank(pin);
|
||||
uint8_t n = (uint8_t) (PINNO(pin));
|
||||
RCC->AHB4ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
|
||||
SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
|
||||
SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
|
||||
SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
|
||||
SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
|
||||
((uint32_t) af) << ((n & 7) * 4));
|
||||
SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
|
||||
}
|
||||
static inline void gpio_input(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 0);
|
||||
}
|
||||
static inline void gpio_output(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 0);
|
||||
}
|
||||
|
||||
// D2 Kernel clock (8.7.21) USART1 defaults to pclk2 (APB2), while USART2,3
|
||||
// default to pclk1 (APB1). Even if using other kernel clocks, the APBx clocks
|
||||
// must be enabled for CPU access, as the kernel clock drives the BRR, not the
|
||||
// APB bus interface
|
||||
static inline void uart_init(USART_TypeDef *uart, unsigned long baud) {
|
||||
uint8_t af = 7; // Alternate function
|
||||
uint16_t rx = 0, tx = 0; // pins
|
||||
uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
|
||||
|
||||
if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
|
||||
if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(17);
|
||||
if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(18);
|
||||
|
||||
if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
|
||||
if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
|
||||
if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
|
||||
|
||||
#if 0 // CONSTANT BAUD RATE FOR REMOTE DEBUGGING WHILE SETTING THE PLL
|
||||
SETBITS(RCC->D2CCIP2R, 7 << 3, 3 << 3); // use HSI for UART1
|
||||
freq = 64000000;
|
||||
#endif
|
||||
|
||||
gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
|
||||
gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
|
||||
uart->CR1 = 0; // Disable this UART
|
||||
uart->BRR = freq / baud; // Set baud rate
|
||||
uart->CR1 = BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
|
||||
}
|
||||
static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
|
||||
uart->TDR = byte;
|
||||
while ((uart->ISR & BIT(7)) == 0) spin(1);
|
||||
}
|
||||
static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int uart_read_ready(USART_TypeDef *uart) {
|
||||
return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
|
||||
}
|
||||
static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
|
||||
return (uint8_t) (uart->RDR & 255);
|
||||
}
|
||||
|
||||
static inline void rng_init(void) {
|
||||
RCC->D2CCIP2R |= RCC_D2CCIP2R_RNGSEL_0; // RNG clock source pll1_q_ck
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG clock
|
||||
RNG->CR = RNG_CR_RNGEN; // Enable RNG
|
||||
}
|
||||
|
||||
static inline uint32_t rng_read(void) {
|
||||
while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
|
||||
return RNG->DR;
|
||||
}
|
||||
|
||||
static inline char chiprev(void) {
|
||||
uint16_t rev = (uint16_t) (((uint32_t) DBGMCU->IDCODE) >> 16);
|
||||
if (rev == 0x1003) return 'Y';
|
||||
if (rev == 0x2003) return 'V';
|
||||
return '?';
|
||||
}
|
||||
|
||||
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
|
||||
static inline void ethernet_init(void) {
|
||||
// Initialise Ethernet. Enable MAC GPIO pins, see UM2411
|
||||
uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),
|
||||
PIN('C', 1), PIN('C', 4), PIN('C', 5),
|
||||
PIN('G', 11), PIN('G', 12), PIN('G', 13)};
|
||||
for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
|
||||
gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
|
||||
GPIO_PULL_NONE, 11); // 11 is the Ethernet function
|
||||
}
|
||||
NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
|
||||
SETBITS(SYSCFG->PMCR, 7 << 21, 4 << 21); // Use RMII (13.3.1)
|
||||
RCC->AHB1ENR |= BIT(15) | BIT(16) | BIT(17); // Enable Ethernet clocks
|
||||
}
|
||||
|
||||
#define UUID ((uint8_t *) UID_BASE) // Unique 96-bit chip ID. TRM 61.1
|
||||
|
||||
// Helper macro for MAC generation
|
||||
#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
|
||||
{ \
|
||||
2, UUID[0] ^ UUID[1], UUID[2] ^ UUID[3], UUID[4] ^ UUID[5], \
|
||||
UUID[6] ^ UUID[7] ^ UUID[8], UUID[9] ^ UUID[10] ^ UUID[11] \
|
||||
}
|
||||
@ -1,29 +0,0 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
|
||||
sram(rwx) : ORIGIN = 0x24000000, LENGTH = 512k
|
||||
}
|
||||
_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
|
||||
|
||||
SECTIONS {
|
||||
.vectors : { KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text* .text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.data : {
|
||||
_sdata = .;
|
||||
*(.first_data)
|
||||
*(.data SORT(.data.*))
|
||||
_edata = .;
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : {
|
||||
_sbss = .;
|
||||
*(.bss SORT(.bss.*) COMMON)
|
||||
_ebss = .;
|
||||
} > sram
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
}
|
||||
@ -1,92 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
#include "net.h"
|
||||
|
||||
#define BLINK_PERIOD_MS 1000 // LED blinking period in millis
|
||||
|
||||
static volatile uint64_t s_ticks; // Milliseconds since boot
|
||||
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
|
||||
s_ticks++;
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) { // Let Mongoose use our uptime function
|
||||
return s_ticks; // Return number of milliseconds since boot
|
||||
}
|
||||
|
||||
bool mg_random(void *buf, size_t len) { // Use on-board RNG
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void timer_fn(void *arg) {
|
||||
gpio_toggle(LED); // Blink LED
|
||||
struct mg_tcpip_if *ifp = arg; // And show
|
||||
const char *names[] = {"down", "up", "req", "ready"}; // network stats
|
||||
MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
|
||||
names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
|
||||
ifp->ndrop, ifp->nerr));
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
gpio_output(LED); // Setup green LED
|
||||
uart_init(UART_DEBUG, 115200); // Initialise debug printf
|
||||
ethernet_init(); // Initialise ethernet pins
|
||||
|
||||
MG_INFO(("Chip revision: %c, max cpu clock: %u MHz", chiprev(),
|
||||
(chiprev() == 'V') ? 480 : 400));
|
||||
MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000));
|
||||
|
||||
struct mg_mgr mgr; // Initialise
|
||||
mg_mgr_init(&mgr); // Mongoose event manager
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level
|
||||
|
||||
mg_ota_boot(); // Call bootloader: continue to load, or boot another FW
|
||||
|
||||
#if MG_OTA == MG_OTA_FLASH
|
||||
// Demonstrate the use of mg_flash_{load/save} functions for keeping device
|
||||
// configuration data on flash. Increment boot count on every boot.
|
||||
struct deviceconfig {
|
||||
uint32_t boot_count;
|
||||
char some_other_data[40];
|
||||
};
|
||||
uint32_t key = 0x12345678; // A unique key, one per data type
|
||||
struct deviceconfig dc = {}; // Initialise to some default values
|
||||
mg_flash_load(NULL, key, &dc, sizeof(dc)); // Load from flash
|
||||
dc.boot_count++; // Increment boot count
|
||||
mg_flash_save(NULL, key, &dc, sizeof(dc)); // And save back
|
||||
MG_INFO(("Boot count: %u", dc.boot_count));
|
||||
#endif
|
||||
|
||||
// Initialise Mongoose network stack
|
||||
struct mg_tcpip_driver_stm32h_data driver_data = {.mdc_cr = 4};
|
||||
struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
|
||||
// Uncomment below for static configuration:
|
||||
// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
|
||||
// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
|
||||
// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
|
||||
.driver = &mg_tcpip_driver_stm32h,
|
||||
.driver_data = &driver_data};
|
||||
mg_tcpip_init(&mgr, &mif);
|
||||
mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
|
||||
|
||||
MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
|
||||
while (mif.state != MG_TCPIP_STATE_READY) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
MG_INFO(("Initialising application..."));
|
||||
web_init(&mgr);
|
||||
|
||||
MG_INFO(("Starting event loop"));
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.c
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.h
|
||||
@ -1,12 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_NEWLIB
|
||||
#define MG_OTA MG_OTA_FLASH
|
||||
#define MG_DEVICE MG_DEVICE_STM32H7
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
#define MG_ENABLE_DRIVER_STM32H 1
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.c
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.h
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/packed_fs.c
|
||||
@ -1,98 +0,0 @@
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
int _fstat(int fd, struct stat *st) {
|
||||
if (fd < 0) return -1;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
extern char _end;
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
unsigned char x = 0, *heap_end = (unsigned char *)((size_t) &x - 512);
|
||||
(void) x;
|
||||
if (heap == NULL) heap = (unsigned char *) &_end;
|
||||
prev_heap = heap;
|
||||
if (heap + incr > heap_end) return (void *) -1;
|
||||
heap += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int mkdir(const char *path, mode_t mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {}
|
||||
|
||||
extern uint64_t mg_now(void);
|
||||
|
||||
int _gettimeofday(struct timeval *tv, void *tz) {
|
||||
uint64_t now = mg_now();
|
||||
(void) tz;
|
||||
tv->tv_sec = (time_t) (now / 1000);
|
||||
tv->tv_usec = (unsigned long) ((now % 1000) * 1000);
|
||||
return 0;
|
||||
}
|
||||
@ -1,53 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// This file contains essentials required by the CMSIS:
|
||||
// uint32_t SystemCoreClock - holds the system core clock value
|
||||
// SystemInit() - initialises the system, e.g. sets up clocks
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
uint32_t SystemCoreClock = CPU_FREQUENCY;
|
||||
|
||||
static inline unsigned int div2prescval(unsigned int div) {
|
||||
// 0 --> /1; 8 --> /2 ... 11 --> /16; 12 --> /64 ... 15 --> /512
|
||||
if (div == 1) return 0;
|
||||
if (div > 16) div /= 2;
|
||||
unsigned int val = 7;
|
||||
while (div >>= 1) ++val;
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned int pllrge(unsigned int f) {
|
||||
unsigned int val = 0;
|
||||
while (f >>= 1) ++val;
|
||||
return val - 1;
|
||||
}
|
||||
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
__DSB();
|
||||
__ISB();
|
||||
// Set flash latency. RM0481, section 7.11.1, section 7.3.4 table 37
|
||||
SETBITS(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
|
||||
FLASH_ACR_LATENCY_7WS | FLASH_ACR_WRHIGHFREQ_1);
|
||||
SETBITS(
|
||||
RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),
|
||||
(div2prescval(D1CPRE) << 8) | (D1PPRE << 4) | (div2prescval(HPRE) << 0));
|
||||
RCC->D2CFGR = (D2PPRE2 << 8) | (D2PPRE1 << 4);
|
||||
RCC->D3CFGR = (D3PPRE << 4);
|
||||
SETBITS(RCC->PLLCFGR, 3 << 2,
|
||||
pllrge(PLL1_HSI / PLL1_M)
|
||||
<< 2); // keep reset config (DIVP1EN, !PLL1VCOSEL), PLL1RGE
|
||||
SETBITS(RCC->PLL1DIVR, (0x7F << 9) | (0x1FF << 0),
|
||||
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0)); // Set PLL1_P PLL1_N
|
||||
SETBITS(RCC->PLLCKSELR, 0x3F << 4,
|
||||
PLL1_M << 4); // Set PLL1_M (source defaults to HSI)
|
||||
RCC->CR |= BIT(24); // Enable PLL1
|
||||
while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR |= (3 << 0); // Set clock source to PLL1
|
||||
while ((RCC->CFGR & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
|
||||
RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; // Enable SYSCFG
|
||||
rng_init();
|
||||
SysTick_Config(CPU_FREQUENCY / 1000);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user