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STM32 OTA support for L475-IOT01 and DISCO-F746

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A smattering of other related changes

CL: STM32 OTA support for L475-IOT01 and DISCO-F746

PUBLISHED_FROM=e7142337086d09ba21437455b22d00db47ab33f1
This commit is contained in:
Deomid Ryabkov 2018-08-17 22:59:51 +03:00 committed by Cesanta Bot
parent 0a3e186f11
commit b84981ad03
1 changed files with 16 additions and 6 deletions
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22
src/common/platforms/arm/arm_exc.c
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@ -27,6 +27,10 @@
#include "mgos_core_dump.h"
#include "mgos_hal.h"
#ifndef MGOS_ENABLE_CORE_DUMP
#define MGOS_ENABLE_CORE_DUMP 1
#endif
struct arm_exc_frame {
uint32_t r0;
uint32_t r1;
@ -53,7 +57,7 @@ struct arm_gdb_reg_file {
uint32_t fpscr;
} __attribute__((packed));
#if ARM_HAVE_FPU
#if ARM_HAVE_FPU && !defined(MGOS_BOOT_BUILD)
static void save_s16_s31(uint32_t *dst) {
__asm volatile(
"\
@ -134,16 +138,20 @@ void arm_exc_handler_bottom(uint8_t isr_no, struct arm_exc_frame *ef,
name = "SysTick";
break;
default: {
#ifndef MGOS_BOOT_BUILD
sprintf(buf, "IRQ%u", isr_no - 16);
#endif
name = buf;
}
}
mgos_cd_printf("\n\n--- Exception %u (%s) ---\n", isr_no, name);
if (rf != NULL) {
mgos_cd_printf(" R0: 0x%08lx R1: 0x%08lx R2: 0x%08lx R3: 0x%08lx\n",
rf->r[0], rf->r[1], rf->r[2], rf->r[3]);
mgos_cd_printf(" R4: 0x%08lx R5: 0x%08lx R6: 0x%08lx R7: 0x%08lx\n",
rf->r[4], rf->r[5], rf->r[6], rf->r[7]);
mgos_cd_printf(
" R%d: 0x%08lx R%d: 0x%08lx R%d: 0x%08lx R%d: 0x%08lx\n", 0,
rf->r[0], 1, rf->r[1], 2, rf->r[2], 3, rf->r[3]);
mgos_cd_printf(
" R%d: 0x%08lx R%d: 0x%08lx R%d: 0x%08lx R%d: 0x%08lx\n", 4,
rf->r[4], 5, rf->r[5], 6, rf->r[6], 7, rf->r[7]);
mgos_cd_printf(" R8: 0x%08lx R9: 0x%08lx R10: 0x%08lx R11: 0x%08lx\n",
rf->r[8], rf->r[9], rf->r[10], rf->r[11]);
mgos_cd_printf(" R12: 0x%08lx SP: 0x%08lx LR: 0x%08lx PC: 0x%08lx\n",
@ -151,7 +159,7 @@ void arm_exc_handler_bottom(uint8_t isr_no, struct arm_exc_frame *ef,
mgos_cd_printf(" PSR: 0x%08lx\n", rf->cpsr);
}
memset(rf->d, 0, sizeof(rf->d));
#if ARM_HAVE_FPU
#if ARM_HAVE_FPU && !defined(MGOS_BOOT_BUILD)
rf->fpscr = ef->fpscr;
memcpy((uint8_t *) rf->d, ef->s, sizeof(ef->s));
print_fpu_regs((uint32_t *) rf->d, 0, ARRAY_SIZE(ef->s));
@ -164,10 +172,12 @@ void arm_exc_handler_bottom(uint8_t isr_no, struct arm_exc_frame *ef,
#else
rf->fpscr = 0;
#endif
#if MGOS_ENABLE_CORE_DUMP
mgos_cd_emit_header();
mgos_cd_emit_section(MGOS_CORE_DUMP_SECTION_REGS, rf, sizeof(*rf));
mgos_cd_emit_section("SRAM", (void *) SRAM_BASE_ADDR, SRAM_SIZE);
mgos_cd_emit_footer();
#endif
#ifdef MGOS_HALT_ON_EXCEPTION
mgos_cd_printf("Halting\n");
while (1) {