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https://github.com/cesanta/mongoose.git
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Merge pull request #1702 from cesanta/stm32driver
Add CR setup, set MDC based on HCLK
This commit is contained in:
Sergey Lyubka
GitHub
commit
db35e6a427
@ -2,6 +2,14 @@
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#if MG_ENABLE_MIP && defined(__arm__)
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#if !defined(MG_STM32_CLK_HSE)
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#define MG_STM32_CLK_HSE 8000000UL
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#endif
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#if !defined(MG_STM32_CLK_HSI)
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#define MG_STM32_CLK_HSI 16000000UL
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#endif
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struct stm32_eth {
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volatile uint32_t MACCR, MACFFR, MACHTHR, MACHTLR, MACMIIAR, MACMIIDR, MACFCR,
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MACVLANTR, RESERVED0[2], MACRWUFFR, MACPMTCSR, RESERVED1, MACDBGR, MACSR,
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@ -34,6 +42,9 @@ static inline void spin(volatile uint32_t count) {
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while (count--) asm("nop");
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}
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static uint32_t hclk_get(void);
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static uint8_t cr_guess(uint32_t hclk);
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static uint32_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ETH->MACMIIAR &= (7 << 2);
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ETH->MACMIIAR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6);
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@ -73,7 +84,7 @@ static bool mip_driver_stm32_init(uint8_t *mac, void *userdata) {
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// hardware checksum. Therefore, descriptor size is 4, not 8
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// ETH->DMABMR = BIT(13) | BIT(16) | BIT(22) | BIT(23) | BIT(25);
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ETH->MACIMR = BIT(3) | BIT(9); // Mask timestamp & PMT IT
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ETH->MACMIIAR = 4 << 2; // MDC clock 150-216 MHz, 38.8.1
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ETH->MACMIIAR = cr_guess(hclk_get()) << 2; // MDC clock
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ETH->MACFCR = BIT(7); // Disable zero quarta pause
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ETH->MACFFR = BIT(31); // Receive all
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY
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@ -144,4 +155,57 @@ struct mip_driver mip_driver_stm32 = {.init = mip_driver_stm32_init,
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.tx = mip_driver_stm32_tx,
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.setrx = mip_driver_stm32_setrx,
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.up = mip_driver_stm32_up};
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/* Calculate HCLK from clock settings,
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valid for STM32F74xxx/75xxx (5.3) and STM32F42xxx/43xxx (6.3) */
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static const uint8_t ahbptab[8] = {1, 2, 3, 4, 6, 7, 8, 9}; // log2(div)
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struct rcc {
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volatile uint32_t CR, PLLCFGR, CFGR;
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};
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#define RCC ((struct rcc *) 0x40023800)
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static uint32_t hclk_get(void) {
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uint32_t clk = 0;
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if (RCC->CFGR & (1 << 2)) {
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clk = MG_STM32_CLK_HSE;
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} else if (RCC->CFGR & (1 << 3)) {
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uint32_t vco, m, n, p;
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m = (RCC->PLLCFGR & (0x3FUL << 0)) >> 0;
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n = (RCC->PLLCFGR & (0x1FFUL << 6)) >> 6;
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p = (((RCC->PLLCFGR & (0x03UL << 16)) >> 16) + 1) * 2;
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if (RCC->PLLCFGR & (1UL << 22))
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clk = MG_STM32_CLK_HSE;
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else
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clk = MG_STM32_CLK_HSI;
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vco = (uint32_t)((uint64_t)(((uint32_t) clk * (uint32_t) n)) /
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((uint32_t) m));
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clk = vco / p;
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} else {
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clk = MG_STM32_CLK_HSI;
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}
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int hpre = (RCC->CFGR & (0x0F << 4)) >> 4;
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if (hpre < 8) return clk;
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return ((uint32_t) clk) >> ahbptab[hpre - 8];
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}
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/* Guess CR from HCLK, set to IEEE802.3 max -5% clock drift;
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valid for STM32F74xxx/75xxx (38.8.1) and STM32F42xxx/43xxx (33.8.1) */
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#define CRDTAB_LEN 6
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static const uint8_t crdtab[CRDTAB_LEN][2] = {
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// [{setting, div ratio},...]
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{2, 16}, {3, 26}, {0, 42}, {1, 62}, {4, 102}, {5, 124},
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};
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static uint8_t cr_guess(uint32_t hclk) {
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MG_DEBUG(("HCLK: %u", hclk));
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if (hclk < 25000000) {
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MG_ERROR(("HCLK too low"));
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return CRDTAB_LEN;
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}
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for (int i = 0; i < CRDTAB_LEN; i++)
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if (hclk / crdtab[i][1] <= 2375000UL) return crdtab[i][0]; // 2.5MHz - 5%
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MG_ERROR(("HCLK too high"));
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return CRDTAB_LEN;
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}
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#endif // MG_ENABLE_MIP
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66
mongoose.c
66
mongoose.c
@ -5973,6 +5973,14 @@ struct mip_driver mip_driver_enc28j60 = {.init = mip_driver_enc28j60_init,
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#if MG_ENABLE_MIP && defined(__arm__)
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#if !defined(MG_STM32_CLK_HSE)
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#define MG_STM32_CLK_HSE 8000000UL
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#endif
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#if !defined(MG_STM32_CLK_HSI)
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#define MG_STM32_CLK_HSI 16000000UL
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#endif
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struct stm32_eth {
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volatile uint32_t MACCR, MACFFR, MACHTHR, MACHTLR, MACMIIAR, MACMIIDR, MACFCR,
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MACVLANTR, RESERVED0[2], MACRWUFFR, MACPMTCSR, RESERVED1, MACDBGR, MACSR,
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@ -6005,6 +6013,9 @@ static inline void spin(volatile uint32_t count) {
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while (count--) asm("nop");
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}
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static uint32_t hclk_get(void);
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static uint8_t cr_guess(uint32_t hclk);
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static uint32_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ETH->MACMIIAR &= (7 << 2);
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ETH->MACMIIAR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6);
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@ -6044,7 +6055,7 @@ static bool mip_driver_stm32_init(uint8_t *mac, void *userdata) {
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// hardware checksum. Therefore, descriptor size is 4, not 8
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// ETH->DMABMR = BIT(13) | BIT(16) | BIT(22) | BIT(23) | BIT(25);
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ETH->MACIMR = BIT(3) | BIT(9); // Mask timestamp & PMT IT
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ETH->MACMIIAR = 4 << 2; // MDC clock 150-216 MHz, 38.8.1
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ETH->MACMIIAR = cr_guess(hclk_get()) << 2; // MDC clock
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ETH->MACFCR = BIT(7); // Disable zero quarta pause
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ETH->MACFFR = BIT(31); // Receive all
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY
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@ -6115,6 +6126,59 @@ struct mip_driver mip_driver_stm32 = {.init = mip_driver_stm32_init,
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.tx = mip_driver_stm32_tx,
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.setrx = mip_driver_stm32_setrx,
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.up = mip_driver_stm32_up};
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/* Calculate HCLK from clock settings,
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valid for STM32F74xxx/75xxx (5.3) and STM32F42xxx/43xxx (6.3) */
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static const uint8_t ahbptab[8] = {1, 2, 3, 4, 6, 7, 8, 9}; // log2(div)
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struct rcc {
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volatile uint32_t CR, PLLCFGR, CFGR;
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};
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#define RCC ((struct rcc *) 0x40023800)
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static uint32_t hclk_get(void) {
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uint32_t clk = 0;
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if (RCC->CFGR & (1 << 2)) {
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clk = MG_STM32_CLK_HSE;
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} else if (RCC->CFGR & (1 << 3)) {
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uint32_t vco, m, n, p;
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m = (RCC->PLLCFGR & (0x3FUL << 0)) >> 0;
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n = (RCC->PLLCFGR & (0x1FFUL << 6)) >> 6;
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p = (((RCC->PLLCFGR & (0x03UL << 16)) >> 16) + 1) * 2;
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if (RCC->PLLCFGR & (1UL << 22))
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clk = MG_STM32_CLK_HSE;
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else
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clk = MG_STM32_CLK_HSI;
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vco = (uint32_t)((uint64_t)(((uint32_t) clk * (uint32_t) n)) /
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((uint32_t) m));
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clk = vco / p;
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} else {
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clk = MG_STM32_CLK_HSI;
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}
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int hpre = (RCC->CFGR & (0x0F << 4)) >> 4;
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if (hpre < 8) return clk;
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return ((uint32_t) clk) >> ahbptab[hpre - 8];
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}
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/* Guess CR from HCLK, set to IEEE802.3 max -5% clock drift;
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valid for STM32F74xxx/75xxx (38.8.1) and STM32F42xxx/43xxx (33.8.1) */
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#define CRDTAB_LEN 6
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static const uint8_t crdtab[CRDTAB_LEN][2] = {
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// [{setting, div ratio},...]
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{2, 16}, {3, 26}, {0, 42}, {1, 62}, {4, 102}, {5, 124},
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};
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static uint8_t cr_guess(uint32_t hclk) {
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MG_DEBUG(("HCLK: %u", hclk));
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if (hclk < 25000000) {
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MG_ERROR(("HCLK too low"));
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return CRDTAB_LEN;
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}
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for (int i = 0; i < CRDTAB_LEN; i++)
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if (hclk / crdtab[i][1] <= 2375000UL) return crdtab[i][0]; // 2.5MHz - 5%
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MG_ERROR(("HCLK too high"));
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return CRDTAB_LEN;
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}
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#endif // MG_ENABLE_MIP
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#ifdef MG_ENABLE_LINES
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