cpq
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d76e69f9a7
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Use UART_DEBUG
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2023-02-01 21:08:24 +00:00 |
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Sergio R. Caprile
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f4d058155a
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Fix UART1,2 clocking in all other examples
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2023-01-20 17:49:57 -03:00 |
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Sergio R. Caprile
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37c0ed0b49
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Fix AF in UART1,2
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2023-01-19 15:28:51 -03:00 |
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Sergio R. Caprile
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2c014778d9
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Minor tweaks in STM32 examples
Fix comments in newer mip initialization (main.c)
Correct stack initialization (boot.c)
Remove SCC clock enable when not needed (mcu.h)
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2022-12-09 15:20:51 -03:00 |
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Sergey Lyubka
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51076e68c8
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Merge pull request #1701 from cesanta/enableFPU
Enable FPU
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2022-09-02 15:46:00 +01:00 |
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Sergio R. Caprile
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3270f1252b
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Enable FPU
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2022-09-02 11:18:11 -03:00 |
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Sergio R. Caprile
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62a6b61fc9
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Fix SCB address for scb struct
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2022-09-01 17:14:31 -03:00 |
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Sergio R. Caprile
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c289556775
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Group clock setup dependencies
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2022-08-29 14:36:40 -03:00 |
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cpq
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dcdeffff9a
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MIP refactor: use mg_hton*, move driver_data to ifp, parametrise f746 PLL setup
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2022-08-27 16:45:31 +01:00 |
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cpq
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8596e1bef7
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Enable FPU
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2022-08-16 16:45:05 +01:00 |
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Sergey Lyubka
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2ae341cf5e
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Add nucleo-f746zg-baremetal
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2022-05-26 13:53:36 +01:00 |
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