15 Commits

Author	SHA1	Message	Date
Sergio R. Caprile	e3d1a69223	CR incorrectly set in STM32 driver	2022-11-02 19:25:05 -03:00
cpq	6a47ff6422	Activate asan for mip_test	2022-09-23 08:35:59 +01:00
cpq	a12bd2271e	Fuzzing MIP	2022-09-21 20:29:49 +01:00
cpq	82b50fd3a5	Pass MDC clock divider explicitly rather than guess	2022-09-12 23:57:04 +01:00
cpq	c718d7999f	Add MAC addr filtering to stm32 driver. Record free space in q profiler	2022-09-10 16:38:03 +01:00
Sergio R. Caprile	313fddf722	Add rudimentary queue profiler ... ETH IRQ and mip_poll() can both write to the queue, so if a memcpy() is interrupted we might see some weird records.	2022-09-07 17:14:03 -03:00
cpq	44b4944334	Use single-line comments	2022-09-03 09:49:41 +01:00
Sergio R. Caprile	4a1a26e8b7	Extend explanation for MDC clock	2022-09-02 15:03:46 -03:00
Sergio R. Caprile	7358ed25a5	Add CR setup, set MDC based on HCLK	2022-09-02 14:02:02 -03:00
cpq	567fccd7ee	Refactor W5500 driver, add arduino w5500 example	2022-09-02 12:58:54 +01:00
cpq	8a61969c8f	Add struct mip_spi for SPI drivers, and skeleton for enc28j60 driver	2022-08-31 08:35:06 +01:00
cpq	dcdeffff9a	MIP refactor: use mg_hton*, move driver_data to ifp, parametrise f746 PLL setup	2022-08-27 16:45:31 +01:00
Sergey Lyubka	c446fe0c6d	Make stm32 eth declared as volatile	2022-06-21 12:11:59 +01:00
Sergey Lyubka	5a448ab4f5	Compile driver_stm32.c only for __arm__	2022-06-13 01:04:09 +01:00
Sergey Lyubka	d3368e4aad	Move mip into mip/	2022-06-11 17:29:45 +01:00