// Copyright (c) 2022 Cesanta Software Limited // All rights reserved // https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf #pragma once #include #include #include #include #include #include "stm32f746xx.h" #define BIT(x) (1UL << (x)) #define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK) #define PIN(bank, num) ((((bank) - 'A') << 8) | (num)) #define PINNO(pin) (pin & 255) #define PINBANK(pin) (pin >> 8) /* System clock 5.3.3: APB1 clock <= 54MHz; APB2 clock <= 108MHz 3.3.2, Table 5: configure flash latency (WS) in accordance to clock freq 38.4: The AHB clock frequency must be at least 25 MHz when the Ethernet controller is used */ enum { APB1_PRE = 5 /* AHB clock / 4 */, APB2_PRE = 4 /* AHB clock / 2 */ }; enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 216, PLL_P = 2, PLL_Q = 9 }; #define FLASH_LATENCY 7 #define SYS_FREQUENCY ((PLL_HSI * PLL_N / PLL_M / PLL_P) * 1000000) // Core 216 MHz, USB 48 MHz #define APB2_FREQUENCY (SYS_FREQUENCY / (BIT(APB2_PRE - 3))) #define APB1_FREQUENCY (SYS_FREQUENCY / (BIT(APB1_PRE - 3))) static inline void spin(volatile uint32_t count) { while (count--) asm("nop"); } static inline void systick_init(uint32_t ticks) { if ((ticks - 1) > 0xffffff) return; // Systick timer is 24 bit SysTick->LOAD = ticks - 1; SysTick->VAL = 0; SysTick->CTRL = BIT(0) | BIT(1) | BIT(2); // Enable systick } #define GPIO(bank) ((GPIO_TypeDef *) (GPIOA_BASE + 0x400U * (bank))) enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG }; enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN }; enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE }; enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN }; static inline void gpio_toggle(uint16_t pin) { GPIO_TypeDef *gpio = GPIO(PINBANK(pin)); uint32_t mask = BIT(PINNO(pin)); gpio->BSRR |= mask << (gpio->ODR & mask ? 16 : 0); } static inline void gpio_write(uint16_t pin, bool val) { GPIO_TypeDef *gpio = GPIO(PINBANK(pin)); gpio->BSRR = (1U << PINNO(pin)) << (val ? 0 : 16); } static inline void gpio_set_mode(uint16_t pin, uint8_t mode) { GPIO_TypeDef *gpio = GPIO(PINBANK(pin)); // GPIO bank int n = PINNO(pin); // Pin number RCC->AHB1ENR |= BIT(PINBANK(pin)); // Enable GPIO clock gpio->MODER &= ~(3U << (n * 2)); // Clear existing setting gpio->MODER |= (mode & 3U) << (n * 2); // Set new mode } static inline void gpio_set_af(uint16_t pin, uint8_t af_num) { GPIO_TypeDef *gpio = GPIO(PINBANK(pin)); // GPIO bank int n = PINNO(pin); // Pin number gpio->AFR[n >> 3] &= ~(15UL << ((n & 7) * 4)); gpio->AFR[n >> 3] |= ((uint32_t) af_num) << ((n & 7) * 4); } static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type, uint8_t speed, uint8_t pull, uint8_t af) { GPIO_TypeDef *gpio = GPIO(PINBANK(pin)); // GPIO bank uint8_t n = (uint8_t) (PINNO(pin)); RCC->AHB1ENR |= BIT(PINBANK(pin)); // Enable GPIO clock SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n); SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2)); SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2)); SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4), ((uint32_t) af) << ((n & 7) * 4)); SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2)); } #define UART1 USART1 #define UART2 USART2 #define UART3 USART3 static inline void uart_init(USART_TypeDef *uart, unsigned long baud) { // https://www.st.com/resource/en/datasheet/stm32f746zg.pdf uint8_t af = 7; // Alternate function uint16_t rx = 0, tx = 0; // pins uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1 if (uart == UART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4); if (uart == UART2) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(17); if (uart == UART3) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(18); if (uart == UART1) tx = PIN('A', 9), rx = PIN('A', 10); if (uart == UART2) tx = PIN('A', 2), rx = PIN('A', 3); if (uart == UART3) tx = PIN('D', 8), rx = PIN('D', 9); gpio_set_mode(tx, GPIO_MODE_AF); gpio_set_af(tx, af); gpio_set_mode(rx, GPIO_MODE_AF); gpio_set_af(rx, af); uart->CR1 = 0; // Disable this UART uart->BRR = freq / baud; // Set baud rate uart->CR1 |= BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE } static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) { uart->TDR = byte; while ((uart->ISR & BIT(7)) == 0) spin(1); } static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) { while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++); } static inline int uart_read_ready(USART_TypeDef *uart) { return uart->ISR & BIT(5); // If RXNE bit is set, data is ready } static inline uint8_t uart_read_byte(USART_TypeDef *uart) { return (uint8_t) (uart->RDR & 255); } static inline void clock_init(void) { // Set clock frequency #if 0 RCC->APB1ENR |= BIT(28); // Power enable PWR->CR1 |= 3UL << 14; // Voltage regulator scale 3 PWR->CR1 |= BIT(16); // Enable overdrive while ((PWR->CSR1 & BIT(16)) == 0) spin(1); // Wait until done PWR->CR1 |= BIT(17); // Enable overdrive switching while ((PWR->CSR1 & BIT(17)) == 0) spin(1); // Wait until done #endif SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU asm("DSB"); asm("ISB"); FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch RCC->PLLCFGR &= ~((BIT(17) - 1) | (0xF << 24)); // Clear PLL multipliers RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P RCC->PLLCFGR |= PLL_M | (PLL_N << 6) | (PLL_Q << 24); // Set PLL_M _N _Q RCC->CR |= BIT(24); // Enable PLL while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done RCC->CFGR = (APB1_PRE << 10) | (APB2_PRE << 13); // Set prescalers RCC->CFGR |= 2; // Set clock source to PLL while ((RCC->CFGR & 12) == 0) spin(1); // Wait until done }