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177 lines
7.3 KiB
C
177 lines
7.3 KiB
C
// Copyright (c) 2022-2024 Cesanta Software Limited
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// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
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// https://www.st.com/resource/en/datasheet/stm32f746zg.pdf
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#pragma once
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#define LED1 PIN('B', 0) // On-board LED pin (green)
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#define LED2 PIN('B', 7) // On-board LED pin (blue)
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#define LED3 PIN('B', 14) // On-board LED pin (red)
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#define UART_DEBUG USART3 // Wired to the on-board st-link debugger
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#include <stm32f746xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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void hal_init(void);
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size_t hal_ram_free(void);
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size_t hal_ram_used(void);
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/* System clock
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5.3.3: APB1 clock <= 54MHz; APB2 clock <= 108MHz
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3.3.2, Table 5: configure flash latency (WS) in accordance to clock freq
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38.4: The AHB clock frequency must be at least 25 MHz when the Ethernet
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controller is used */
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enum { APB1_PRE = 5 /* AHB clock / 4 */, APB2_PRE = 4 /* AHB clock / 2 */ };
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enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 216, PLL_P = 2 }; // Run at 216 Mhz
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#define FLASH_LATENCY 7
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#define SYS_FREQUENCY ((PLL_HSI * PLL_N / PLL_M / PLL_P) * 1000000)
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#define APB2_FREQUENCY (SYS_FREQUENCY / (BIT(APB2_PRE - 3)))
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#define APB1_FREQUENCY (SYS_FREQUENCY / (BIT(APB1_PRE - 3)))
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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#define GPIO(N) ((GPIO_TypeDef *) (0x40020000 + 0x400 * (N)))
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static GPIO_TypeDef *gpio_bank(uint16_t pin) {
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return GPIO(PINBANK(pin));
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}
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static inline void gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int gpio_read(uint16_t pin) {
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return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->AHB1ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
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CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void irq_exti_attach(uint16_t pin) {
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uint8_t bank = (uint8_t) (PINBANK(pin)), n = (uint8_t) (PINNO(pin));
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SYSCFG->EXTICR[n / 4] &= ~(15UL << ((n % 4) * 4));
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SYSCFG->EXTICR[n / 4] |= (uint32_t) (bank << ((n % 4) * 4));
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EXTI->IMR |= BIT(n);
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EXTI->RTSR |= BIT(n);
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EXTI->FTSR |= BIT(n);
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int irqvec = n < 5 ? 6 + n : n < 10 ? 23 : 40; // IRQ vector index, 10.1.2
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NVIC_SetPriority(irqvec, 3);
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NVIC_EnableIRQ(irqvec);
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}
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static inline void uart_init(USART_TypeDef *uart, unsigned long baud) {
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uint8_t af = 7; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
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if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
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if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(17);
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if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(18);
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if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
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if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
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if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
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gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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uart->CR1 = 0; // Disable this UART
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uart->BRR = freq / baud; // Set baud rate
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uart->CR1 |= BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
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}
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static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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uart->TDR = byte;
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while ((uart->ISR & BIT(7)) == 0) (void) 0;
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}
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static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(USART_TypeDef *uart) {
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return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->RDR & 255);
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}
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static inline void rng_init(void) {
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RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;
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RNG->CR |= RNG_CR_RNGEN;
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}
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static inline uint32_t rng_read(void) {
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while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
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return RNG->DR;
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}
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static inline void ethernet_init(void) {
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// Initialise Ethernet. Enable MAC GPIO pins, see
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// https://www.farnell.com/datasheets/2014265.pdf section 6.10
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uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),
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PIN('B', 13), PIN('C', 1), PIN('C', 4),
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PIN('C', 5), PIN('G', 11), PIN('G', 13)};
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for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
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gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
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GPIO_PULL_NONE, 11); // 11 is the Ethernet function
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}
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; // Enable SYSCFG
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NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
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SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; // Use RMII. Goes first!
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RCC->AHB1ENR |=
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RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN;
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}
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static inline void clock_init(void) {
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
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__DSB();
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__ISB();
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FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch
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RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers
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RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P
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RCC->PLLCFGR |= PLL_M | (PLL_N << 6); // Set PLL_M and PLL_N
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RCC->CR |= BIT(24); // Enable PLL
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while ((RCC->CR & BIT(25)) == 0) (void) 0; // Wait until done
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RCC->CFGR = (APB1_PRE << 10) | (APB2_PRE << 13); // Set prescalers
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RCC->CFGR |= 2; // Set clock source to PLL
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while ((RCC->CFGR & 12) == 0) (void) 0; // Wait until done
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}
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// Helper macro for MAC generation
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#define UUID ((uint8_t *) UID_BASE) // Unique 96-bit chip ID. TRM 41.1
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#define GENERATE_MAC_ADDRESS() \
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{ \
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2, UUID[0] ^ UUID[1], UUID[2] ^ UUID[3], UUID[4] ^ UUID[5], \
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UUID[6] ^ UUID[7] ^ UUID[8], UUID[9] ^ UUID[10] ^ UUID[11] \
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}
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