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https://github.com/cesanta/mongoose.git
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219 lines
8.5 KiB
C
219 lines
8.5 KiB
C
// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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/* System clock
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5.3.3: APB1 clock <= 54MHz; APB2 clock <= 108MHz
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3.3.2, Table 5: configure flash latency (WS) in accordance to clock freq
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38.4: The AHB clock frequency must be at least 25 MHz when the Ethernet controller is used */
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enum { APB1_PRE = 5 /* AHB clock / 4 */, APB2_PRE = 4 /* AHB clock / 2 */ };
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enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 216, PLL_P = 2 }; // Run at 216 Mhz
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//#define PLL_FREQ PLL_HSI
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#define PLL_FREQ (PLL_HSI * PLL_N / PLL_M / PLL_P)
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#define FLASH_LATENCY 7
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#define FREQ (PLL_FREQ * 1000000)
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static inline void spin(volatile uint32_t count) {
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while (count--) asm("nop");
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}
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struct rcc {
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volatile uint32_t CR, PLLCFGR, CFGR, CIR, AHB1RSTR, AHB2RSTR, AHB3RSTR,
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RESERVED0, APB1RSTR, APB2RSTR, RESERVED1[2], AHB1ENR, AHB2ENR, AHB3ENR,
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RESERVED2, APB1ENR, APB2ENR, RESERVED3[2], AHB1LPENR, AHB2LPENR,
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AHB3LPENR, RESERVED4, APB1LPENR, APB2LPENR, RESERVED5[2], BDCR, CSR,
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RESERVED6[2], SSCGR, PLLI2SCFGR, PLLSAICFGR, DCKCFGR1, DCKCFGR2;
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};
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#define RCC ((struct rcc *) 0x40023800)
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struct pwr {
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volatile uint32_t CR1, CSR1, CR2, CSR2;
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};
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#define PWR ((struct pwr *) 0x40007000)
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struct nvic {
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volatile uint32_t ISER[8], RESERVED0[24], ICER[8], RSERVED1[24], ISPR[8],
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RESERVED2[24], ICPR[8], RESERVED3[24], IABR[8], RESERVED4[56], IP[240],
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RESERVED5[644], STIR;
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};
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#define NVIC ((struct nvic *) 0xe000e100)
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static inline void nvic_set_prio(int irq, uint32_t prio) {
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NVIC->IP[irq] = prio << 4;
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}
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static inline void nvic_enable_irq(int irq) {
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NVIC->ISER[irq >> 5] = (uint32_t) (1 << (irq & 31));
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}
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struct systick {
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volatile uint32_t CTRL, LOAD, VAL, CALIB;
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};
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#define SYSTICK ((struct systick *) 0xe000e010) // 2.2.2
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static inline void systick_init(uint32_t ticks) {
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if ((ticks - 1) > 0xffffff) return; // Systick timer is 24 bit
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SYSTICK->LOAD = ticks - 1;
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SYSTICK->VAL = 0;
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SYSTICK->CTRL = BIT(0) | BIT(1) | BIT(2); // Enable systick
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}
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struct flash {
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volatile uint32_t ACR, KEYR, OPTKEYR, SR, CR, AR, RESERVED, OBR, WRPR;
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};
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#define FLASH ((struct flash *) 0x40023c00)
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struct scb {
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volatile uint32_t CPUID, ICSR, VTOR, AIRCR, SCR, CCR, SHPR[3], SHCSR, CFSR,
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HFSR, DFSR, MMFAR, BFAR, AFSR, ID_PFR[2], ID_DFR, ID_AFR, ID_MFR[4],
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ID_ISAR[5], RESERVED0[1], CLIDR, CTR, CCSIDR, CSSELR, CPACR,
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RESERVED3[93], STIR, RESERVED4[15], MVFR0, MVFR1, MVFR2, RESERVED5[1],
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ICIALLU, RESERVED6[1], ICIMVAU, DCIMVAC, DCISW, DCCMVAU, DCCMVAC, DCCSW,
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DCCIMVAC, DCCISW, RESERVED7[6], ITCMCR, DTCMCR, AHBPCR, CACR, AHBSCR,
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RESERVED8[1], ABFSR;
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};
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#define SCB ((struct scb *) 0xe000ed00)
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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struct gpio {
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volatile uint32_t MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFR[2];
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};
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#define GPIO(N) ((struct gpio *) (0x40020000 + 0x400 * (N)))
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static struct gpio *gpio_bank(uint16_t pin) {
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return GPIO(PINBANK(pin));
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}
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static inline void gpio_toggle(uint16_t pin) {
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struct gpio *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR |= mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int gpio_read(uint16_t pin) {
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return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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struct gpio *gpio = gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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struct gpio *gpio = gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->AHB1ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
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SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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struct syscfg {
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volatile uint32_t MEMRMP, PMC, EXTICR[4], RESERVED[2], CMPCR;
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};
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#define SYSCFG ((struct syscfg *) 0x40013800)
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struct exti {
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volatile uint32_t IMR, EMR, RTSR, FTSR, SWIER, PR;
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};
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#define EXTI ((struct exti *) 0x40013c00)
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static inline void irq_exti_attach(uint16_t pin) {
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uint8_t bank = (uint8_t) (PINBANK(pin)), n = (uint8_t) (PINNO(pin));
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RCC->APB2ENR |= BIT(14); // Enable SYSCFG
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SYSCFG->EXTICR[n / 4] &= ~(15UL << ((n % 4) * 4));
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SYSCFG->EXTICR[n / 4] |= (uint32_t) (bank << ((n % 4) * 4));
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EXTI->IMR |= BIT(n);
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EXTI->RTSR |= BIT(n);
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EXTI->FTSR |= BIT(n);
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int irqvec = n < 5 ? 6 + n : n < 10 ? 23 : 40; // IRQ vector index, 10.1.2
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nvic_set_prio(irqvec, 3);
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nvic_enable_irq(irqvec);
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}
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struct uart {
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volatile uint32_t CR1, CR2, CR3, BRR, GTPR, RTOR, RQR, ISR, ICR, RDR, TDR;
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};
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#define UART1 ((struct uart *) 0x40011000)
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#define UART2 ((struct uart *) 0x40004400)
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#define UART3 ((struct uart *) 0x40004800)
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static inline void uart_init(struct uart *uart, unsigned long baud) {
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// https://www.st.com/resource/en/datasheet/stm32f746zg.pdf
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uint8_t af = 7; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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if (uart == UART1) RCC->APB2ENR |= BIT(4);
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if (uart == UART2) RCC->APB1ENR |= BIT(17);
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if (uart == UART3) RCC->APB1ENR |= BIT(18);
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if (uart == UART1) tx = PIN('A', 9), rx = PIN('A', 10);
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if (uart == UART2) tx = PIN('A', 2), rx = PIN('A', 3);
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if (uart == UART3) tx = PIN('D', 8), rx = PIN('D', 9);
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gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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uart->CR1 = 0; // Disable this UART
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uart->BRR = FREQ / 4 / baud; // Baud rate, "4" is APBx prescaler, different from APBx_PRE
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// TODO(): make this configurable ?
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uart->CR1 |= BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
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}
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static inline void uart_write_byte(struct uart *uart, uint8_t byte) {
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uart->TDR = byte;
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while ((uart->ISR & BIT(7)) == 0) spin(1);
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}
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static inline void uart_write_buf(struct uart *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(struct uart *uart) {
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return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(struct uart *uart) {
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return (uint8_t) (uart->RDR & 255);
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}
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static inline void clock_init(void) { // Set clock frequency
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#if 0
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RCC->APB1ENR |= BIT(28); // Power enable
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PWR->CR1 |= 3UL << 14; // Voltage regulator scale 3
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PWR->CR1 |= BIT(16); // Enable overdrive
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while ((PWR->CSR1 & BIT(16)) == 0) spin(1); // Wait until done
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PWR->CR1 |= BIT(17); // Enable overdrive switching
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while ((PWR->CSR1 & BIT(17)) == 0) spin(1); // Wait until done
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#endif
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
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asm ("DSB");
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asm ("ISB");
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FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch
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RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers
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RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P
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RCC->PLLCFGR |= PLL_M | (PLL_N << 6); // Set PLL_M and PLL_N
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RCC->CR |= BIT(24); // Enable PLL
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while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done
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RCC->CFGR = (APB1_PRE << 10) | (APB2_PRE << 13); // Set prescalers
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RCC->CFGR |= 2; // Set clock source to PLL
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while ((RCC->CFGR & 12) == 0) spin(1); // Wait until done
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}
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