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https://github.com/cesanta/mongoose.git
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224 lines
9.1 KiB
C
224 lines
9.1 KiB
C
// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define LED1 PIN(0, 10)
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#define LED2 PIN(0, 27)
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#define LED3 PIN(1, 2)
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#ifndef UART_DEBUG
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#define UART_DEBUG LPUART4
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#endif
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#include "MCXN947_cm33_core0.h"
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#define BIT(x) (1UL << (x))
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define PIN(bank, num) ((bank << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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void hal_init(void);
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size_t hal_ram_free(void);
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size_t hal_ram_used(void);
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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#define SYS_FREQUENCY 150000000UL
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_HIGH };
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enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP };
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static inline GPIO_Type *gpio_bank(uint16_t pin) {
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static GPIO_Type *const g[] = GPIO_BASE_PTRS;
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return g[PINBANK(pin)];
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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static PORT_Type *const p[] = PORT_BASE_PTRS;
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PORT_Type *port = p[PINBANK(pin)];
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GPIO_Type *gpio = gpio_bank(pin);
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uint32_t mask = (uint32_t) BIT(PINNO(pin));
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bool dopull = pull > 0;
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if (dopull) --pull;
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if (gpio != GPIO5) {
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SYSCON->AHBCLKCTRL0 |=
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(1 << (SYSCON_AHBCLKCTRL0_GPIO0_SHIFT + PINBANK(pin))) |
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(1 << (SYSCON_AHBCLKCTRL0_PORT0_SHIFT + PINBANK(pin)));
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};
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port->PCR[PINNO(pin)] = PORT_PCR_IBE(1) | PORT_PCR_MUX(af) | PORT_PCR_DSE(1) |
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PORT_PCR_ODE(type) |
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PORT_PCR_SRE(speed != GPIO_SPEED_HIGH) |
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PORT_PCR_PE(dopull) | PORT_PCR_PS(pull);
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gpio->ICR[PINNO(pin)] = GPIO_ICR_ISF_MASK;
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if (mode == GPIO_MODE_INPUT) {
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gpio->PDDR &= ~mask;
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} else {
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gpio->PDDR |= mask;
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}
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
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GPIO_PULL_NONE, 0);
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}
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static inline bool gpio_read(uint16_t pin) {
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GPIO_Type *gpio = gpio_bank(pin);
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return gpio->PDR[PINNO(pin)];
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}
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static inline void gpio_write(uint16_t pin, bool value) {
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GPIO_Type *gpio = gpio_bank(pin);
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if (value) {
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gpio->PDR[PINNO(pin)] = 1;
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} else {
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gpio->PDR[PINNO(pin)] = 0;
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}
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}
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static inline void gpio_toggle(uint16_t pin) {
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GPIO_Type *gpio = gpio_bank(pin);
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uint32_t mask = (uint32_t) BIT(PINNO(pin));
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gpio->PTOR = mask;
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}
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// MCU-Link UART (P1_9/8; FC4_P1/0)
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// Arduino J1_2/4 UART (P4_3/2; FC2_P3/2)
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// 33.3.23 LP_FLEXCOMM clocking
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// 66.2.4 LP_FLEXCOMM init
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// 66.5 LPUART
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static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
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static LP_FLEXCOMM_Type *const f[] = LP_FLEXCOMM_BASE_PTRS;
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uint8_t af = 2, fc = 0; // Alternate function, FlexComm instance
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uint16_t pr = 0, pt = 0; // pins
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uint32_t freq = 12000000; // fro_12_m
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if (uart == LPUART2) fc = 2, pt = PIN(4, 3), pr = PIN(4, 2);
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if (uart == LPUART4) fc = 4, pt = PIN(1, 9), pr = PIN(1, 8);
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SYSCON->AHBCLKCTRL1 |= (1 << (SYSCON_AHBCLKCTRL1_FC0_SHIFT + fc));
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SYSCON->PRESETCTRL1 |= (1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc));
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SYSCON->PRESETCTRL1 &= ~(1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc));
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SYSCON->FCCLKSEL[fc] = SYSCON_FCCLKSEL_SEL(2); // clock from FRO_12M / 1
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SYSCON->FLEXCOMMCLKDIV[fc] = SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(0);
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LP_FLEXCOMM_Type *flexcomm = f[fc];
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flexcomm->PSELID = LP_FLEXCOMM_PSELID_PERSEL(1); // configure as UART
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gpio_init(pt, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
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GPIO_PULL_UP, af);
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gpio_init(pr, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
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GPIO_PULL_UP, af);
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uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
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uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
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// use a weird oversample ratio of 26x to fit specs, standard 16x won't do
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CLRSET(uart->BAUD,
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LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK,
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LPUART_BAUD_OSR(26 - 1) | LPUART_BAUD_SBR(freq / (26 * baud)));
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CLRSET(uart->CTRL,
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LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
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LPUART_CTRL_IDLECFG_MASK,
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LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) |
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LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit
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uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
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}
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static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
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uart->DATA = byte;
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while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
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}
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static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline void rng_init(void) {
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}
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static inline uint32_t rng_read(void) {
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return 42;
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}
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// - PHY and MAC clocked via a 50MHz oscillator, P1_4 (ENET0_TXCLK)
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// - 33.3.30 ENET clocking
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// - SMI clocked from AHB module clock (CSR)
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// - PHY RST connected to P5_8
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// - PHY RXD0,1,DV = 1 on RST enable autonegotiation, no hw pull-ups
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static inline void ethernet_init(void) {
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// '0' in clk_rmii, set for RMII mode
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SYSCON->ENETRMIICLKSEL = SYSCON_ENETRMIICLKSEL_SEL(0);
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SYSCON->ENETRMIICLKDIV = SYSCON_ENETRMIICLKDIV_DIV(0);
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SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_ENET_MASK; // enable bus clk
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SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK; // reset MAC
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SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK; // then set RMII
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SYSCON0->ENET_PHY_INTF_SEL |= SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_MASK;
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gpio_init(PIN(5, 8), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
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GPIO_PULL_NONE, 0); // set P5_8 as GPIO (PHY \RST)
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gpio_write(PIN(5, 8), 0); // reset PHY
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gpio_init(PIN(1, 4), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 9); // set P1_4 as ENET0_TXCLK
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gpio_init(PIN(1, 5), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 9); // set P1_5 as ENET0_TXEN
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gpio_init(PIN(1, 6), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 9); // set P1_6 as ENET0_TXD0
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gpio_init(PIN(1, 7), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 9); // set P1_7 as ENET0_TXD1
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gpio_init(PIN(1, 13), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_UP, 9); // set P1_13 as ENET0_RXDV
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gpio_init(PIN(1, 14), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_UP, 9); // set P1_14 as ENET0_RXD0
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gpio_init(PIN(1, 15), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_UP, 9); // set P1_15 as ENET0_RXD1
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gpio_init(PIN(1, 20), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 9); // set P1_20 as ENET0_MDC
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gpio_init(PIN(1, 21), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 9); // set P1_21 as ENET0_MDIO
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spin(10000); // keep PHY RST low for a while
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gpio_write(PIN(5, 8), 1); // deassert RST
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NVIC_EnableIRQ(ETHERNET_IRQn); // Setup Ethernet IRQ handler
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}
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#include "fsl_clock.h"
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#include "fsl_spc.h"
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// 33.2 Figure 127 SCG main clock
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static inline void clock_init(void) {
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SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_SCG_MASK; // enable SCG clk
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CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(2)); // clock main_clock
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spc_active_mode_dcdc_option_t dcdc = {
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.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
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.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength};
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SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdc); // Set DCDC to 1.2 V
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spc_active_mode_core_ldo_option_t ldo = {
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.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
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.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength};
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SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo); // Set LDO_CORE to 1.2 V
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CLRSET(FMU0->FCTRL, FMU_FCTRL_RWSC_MASK, FMU_FCTRL_RWSC(3)); // Set Flash WS
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spc_sram_voltage_config_t sram = {.operateVoltage = kSPC_sramOperateAt1P2V,
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.requestVoltageUpdate = true};
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SPC_SetSRAMOperateVoltage(SPC0, &sram); // Set SRAM timing for 1.2V
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CLOCK_SetupFROHFClocking(48000000U); // Enable FRO HF
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const pll_setup_t pll0 = {.pllctrl = SCG_APLLCTRL_SOURCE(1U) |
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SCG_APLLCTRL_SELI(27U) |
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SCG_APLLCTRL_SELP(13U),
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.pllndiv = SCG_APLLNDIV_NDIV(8U),
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.pllpdiv = SCG_APLLPDIV_PDIV(1U),
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.pllmdiv = SCG_APLLMDIV_MDIV(50U),
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.pllRate = 150000000U};
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CLOCK_SetPLL0Freq(&pll0); // Setup PLL0 (APLL),
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CLOCK_SetPll0MonitorMode(0); // disable monitor mode
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CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(5)); // clock main_clock
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SYSCON->AHBCLKDIV = SYSCON_AHBCLKDIV_DIV(0); // /1
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}
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