mirror of
https://github.com/cesanta/mongoose.git
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338 lines
14 KiB
C
338 lines
14 KiB
C
// Copyright (c) 2024 Cesanta Software Limited
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// All rights reserved
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// https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM
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// https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKBHUG
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#pragma once
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#include "MIMXRT1176_cm7.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - '0') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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// Use LED for blinking, D6: GPIO_AD_04. GPIO3.3 (schematics, RM)
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#define LED PIN('3', 3)
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#ifndef UART_DEBUG
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#define UART_DEBUG LPUART1
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#endif
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// No settable constants, see sysinit.c
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#define SYS_FREQUENCY 996000000UL
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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// Use "Unassigned/Domain Mode"
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static inline void clock_periph(uint32_t index, bool val) {
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CCM->LPCG[index].DIRECT = val ? 1 : 0; // (15.9.1.25)
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}
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// which peripheral feeds the pin
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static inline void gpio_mux_config(uint16_t index, uint8_t af) {
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IOMUXC->SW_MUX_CTL_PAD[index] = af;
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}
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// which pin feeds the peripheral (2nd stage)
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static inline void periph_mux_config(uint16_t index, uint8_t in) {
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IOMUXC->SELECT_INPUT[index] = in;
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}
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// CM7_GPIOx not supported
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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static inline GPIO_Type *gpio_bank(uint16_t pin) {
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static const GPIO_Type *g[] = {NULL, GPIO1, GPIO2, GPIO3, GPIO4,
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GPIO5, GPIO6, GPIO7, GPIO8, GPIO9,
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GPIO10, GPIO11, GPIO12, GPIO13};
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return (GPIO_Type *) g[PINBANK(pin)];
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}
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// pin driver/pull-up/down configuration (allow both cores)
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static inline void gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed,
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uint8_t pull) {
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if (index < kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 ||
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(index >= kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 &&
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index < kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00)) {
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IOMUXC->SW_PAD_CTL_PAD[index] =
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IOMUXC_SW_PAD_CTL_PAD_PDRV(speed == GPIO_SPEED_LOW) |
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IOMUXC_SW_PAD_CTL_PAD_ODE(type) | IOMUXC_SW_PAD_CTL_PAD_PULL(pull);
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} else {
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bool dopull = pull > 0;
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if (dopull) pull = (pull == GPIO_PULL_UP);
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IOMUXC->SW_PAD_CTL_PAD[index] =
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IOMUXC_SW_PAD_CTL_PAD_DSE(speed != GPIO_SPEED_LOW) |
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IOMUXC_SW_PAD_CTL_PAD_ODE(type) | IOMUXC_SW_PAD_CTL_PAD_PUE(dopull) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(pull) |
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IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH);
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}
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull) {
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GPIO_Type *gpio = gpio_bank(pin);
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uint8_t bit = (uint8_t) PINNO(pin);
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uint32_t mask = (uint32_t) BIT(PINNO(pin));
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clock_periph(51, 1); // clk_enable_gpio (15.5.4 Table 15-5)
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clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
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switch (PINBANK(pin)) { // (11.1.1 Table 11-1)
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case 1:
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 + bit, 5);
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 + bit, type, speed,
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pull);
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break;
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case 2:
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IOMUXC_GPR->GPR40 = 0; // select GPIO2
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IOMUXC_GPR->GPR41 = 0; // select GPIO2
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 + bit, 5);
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 + bit, type, speed,
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pull);
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break;
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case 3:
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IOMUXC_GPR->GPR42 = 0; // select GPIO3
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IOMUXC_GPR->GPR43 = 0; // select GPIO3
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 + bit, 5);
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 + bit, type, speed,
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pull);
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break;
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case 4:
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 + bit, 5);
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 + bit, type, speed,
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pull);
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break;
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default:
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// TODO(): support GPIO5-13, 10-15 requires redefinition of PIN() macro
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break;
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}
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gpio->IMR &= ~mask;
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if (mode == GPIO_MODE_INPUT) {
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gpio->GDIR &= ~mask;
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} else {
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gpio->GDIR |= mask;
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}
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
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GPIO_PULL_NONE);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
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GPIO_PULL_NONE);
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}
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static inline bool gpio_read(uint16_t pin) {
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GPIO_Type *gpio = gpio_bank(pin);
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uint32_t mask = (uint32_t) BIT(PINNO(pin));
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return gpio->DR & mask;
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}
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static inline void gpio_write(uint16_t pin, bool value) {
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GPIO_Type *gpio = gpio_bank(pin);
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uint32_t mask = (uint32_t) BIT(PINNO(pin));
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if (value) {
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gpio->DR |= mask;
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} else {
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gpio->DR &= ~mask;
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}
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}
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static inline void gpio_toggle(uint16_t pin) {
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gpio_write(pin, !gpio_read(pin));
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}
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// 15.3 Table 15-2: uart_clk_root
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// 15.4: lpuart*_clk_root 15.5.3 Table 15-4; 15.9.1.2; select OSC_24M
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static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
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uint8_t af = 0; // Alternate function
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uint16_t mr = 0, pr = 0, mt = 0, pt = 0; // pins
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uint32_t freq = 24000000; // uart_clk_root frequency
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if (uart == LPUART1) {
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af = 0;
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mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24;
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pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24;
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mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25;
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pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25;
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// configure clock root source and divisor /1, enable peripheral clock
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CCM->CLOCK_ROOT[25].CONTROL =
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CCM_CLOCK_ROOT_CONTROL_MUX(1) | CCM_CLOCK_ROOT_CONTROL_DIV(0);
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clock_periph(86, 1); // (15.5.4 Table 15-5)
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periph_mux_config(kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT, 0);
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periph_mux_config(kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT, 0);
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} else if (uart == LPUART2) {
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af = 2;
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mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10;
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pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10;
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mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11;
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pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11;
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CCM->CLOCK_ROOT[26].CONTROL =
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CCM_CLOCK_ROOT_CONTROL_MUX(1) | CCM_CLOCK_ROOT_CONTROL_DIV(0);
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clock_periph(87, 1); // (15.5.4 Table 15-5)
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}
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clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
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gpio_mux_config(mt, af);
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gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_NONE);
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gpio_mux_config(mr, af);
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gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
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uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
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uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
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uart->BAUD = LPUART_BAUD_OSR(16 - 1) |
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LPUART_BAUD_SBR(freq / (16 * baud)); // Rx sample at 16x
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uart->CTRL = LPUART_CTRL_IDLECFG(1) |
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LPUART_CTRL_ILT(1); // no parity, idle 2 chars after 1 stop bit
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uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
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}
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static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
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uart->DATA = byte;
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while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
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}
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static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(LPUART_Type *uart) {
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(void) uart;
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return uart->STAT & LPUART_STAT_RDRF_MASK;
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}
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static inline uint8_t uart_read_byte(LPUART_Type *uart) {
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return (uint8_t) (uart->DATA & 255);
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}
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static inline void lpsr_mux_config(uint16_t index, uint8_t af) {
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IOMUXC_LPSR->SW_MUX_CTL_PAD[index] = af;
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}
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static inline void lpsr_pad_config(uint16_t index, uint8_t type, uint8_t speed,
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uint8_t pull) {
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bool dopull = pull > 0;
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if (dopull) pull = (pull == GPIO_PULL_UP);
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IOMUXC_LPSR->SW_PAD_CTL_PAD[index] =
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IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(speed != GPIO_SPEED_LOW) |
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IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(type) |
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IOMUXC_SW_PAD_CTL_PAD_PUE(dopull) | IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(pull) |
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IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH);
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}
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#include "fsl_clock.h"
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// - 15.4 clock tree
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// - 15.3 Table 15-2: ENET1_CLK_ROOT <= 50MHz
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// - PHY has no xtal, XI driven from ENET_REF_CLK (labeled as ENET_TX_REF_CLK
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// (GPIO_DISP_B2_05)), generated by the MCU
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// - PHY RST connected to GPIO12.12 (GPIO_LPSR_12);
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// - 60.4 REF_CLK is RMII mode reference clock for Rx, Tx, and SMI; it is I/O
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static inline void ethernet_init(void) {
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const clock_sys_pll1_config_t pll1 = {.pllDiv2En = true};
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CLOCK_InitSysPll1(&pll1); // setup PLL1 and clock ENET from it
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// configure clock root source PLL1/2 and divisor /10, enable peripheral clock
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CCM->CLOCK_ROOT[51].CONTROL =
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CCM_CLOCK_ROOT_CONTROL_MUX(4) | CCM_CLOCK_ROOT_CONTROL_DIV(10 - 1);
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clock_periph(112, 1); // clk_enable_enet (15.5.4 Table 15-5)
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clock_periph(51, 1); // clk_enable_gpio (15.5.4 Table 15-5)
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clock_periph(50, 1); // clk_enable_iomuxc_lpsr (15.5.4 Table 15-5)
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clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
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lpsr_mux_config(kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12,
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10); // set GPIO12.12 as GPIO (PHY \RST)
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lpsr_pad_config(kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12,
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GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
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GPIO12->IMR &= ~BIT(12);
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GPIO12->GDIR |= BIT(12);
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GPIO12->DR &= ~BIT(12); // reset PHY
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05,
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2); // set for ENET_REF_CLK
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IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05] |=
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IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
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periph_mux_config(kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT,
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1); // drive peripheral from DISP_B2_05, so RMII clock is
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// taken from ENET_REF_CLK
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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IOMUXC_GPR->GPR4 |=
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IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(1); // Set ENET_REF_CLK as output
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06,
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1); // set for RXDATA0
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periph_mux_config(kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0,
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1); // drive peripheral from DISP_B2_06
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07,
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1); // set for RXDATA1
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periph_mux_config(kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1,
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1); // drive peripheral from DISP_B2_07
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08, 1); // set for CRS
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periph_mux_config(kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT,
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1); // drive peripheral from DISP_B2_08
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09, 1); // set for RXERR
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periph_mux_config(kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT,
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1); // drive peripheral from DISP_B2_09
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02,
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1); // set for TXDATA0
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03,
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1); // set for TXDATA1
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04, 1); // set for TXEN
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32, 3); // set for MDC
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_MEDIUM, GPIO_PULL_NONE);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33, 3); // set for MDIO
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periph_mux_config(kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT,
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1); // drive peripheral from AD_33
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
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IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_ENET_MASK; // ERR050396
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gpio_init(PIN('3', 11), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM,
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GPIO_PULL_UP); // setup IRQ (pulled-up)(not used)
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spin(10000); // keep PHY RST low for a while
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GPIO12->DR |= BIT(12); // deassert RST
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clock_periph(112, 1); // clk_enable_enet (15.5.4 Table 15-5)
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NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler
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}
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// Helper macro for MAC generation, byte reads not allowed
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ \
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2, OCOTP->FUSEN[16].FUSE & 255, (OCOTP->FUSEN[16].FUSE >> 10) & 255, \
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((OCOTP->FUSEN[16].FUSE >> 19) ^ (OCOTP->FUSEN[17].FUSE >> 19)) & 255, \
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(OCOTP->FUSEN[17].FUSE >> 10) & 255, OCOTP->FUSEN[17].FUSE & 255 \
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}
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static inline void flash_init(void) { // QSPI in FlexSPI
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// set pins
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clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
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#if 0
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#endif
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}
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