mirror of
https://github.com/cesanta/mongoose.git
synced 2024-12-15 18:09:15 +08:00
279 lines
11 KiB
C
279 lines
11 KiB
C
// Copyright (c) 2022-2023 Cesanta Software Limited
|
|
// All rights reserved
|
|
//
|
|
// Datasheet: RM0433, devboard manual: UM2407
|
|
// https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
|
|
// Alternate functions: https://www.st.com/resource/en/datasheet/stm32h743vi.pdf
|
|
|
|
#pragma once
|
|
|
|
#include <stdbool.h>
|
|
#include <stdint.h>
|
|
#include <stdio.h>
|
|
#include <string.h>
|
|
|
|
#define BIT(x) (1UL << (x))
|
|
#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
|
|
#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
|
|
#define PINNO(pin) (pin & 255)
|
|
#define PINBANK(pin) (pin >> 8)
|
|
|
|
// System clock (2.1, Figure 1; 8.5, Figure 45; 8.5.5, Figure 47; 8.5.6, Figure
|
|
// 49) CPU_FREQUENCY <= 480 MHz; hclk = CPU_FREQUENCY / HPRE ; hclk <= 240 MHz;
|
|
// APB clocks <= 120 MHz. D1 domain bus matrix (and so flash) runs at hclk
|
|
// frequency. Configure flash latency (WS) in accordance to hclk freq (4.3.8,
|
|
// Table 17) The Ethernet controller is in D2 domain and runs at hclk frequency
|
|
enum {
|
|
D1CPRE = 1, // actual divisor value
|
|
HPRE = 2, // actual divisor value
|
|
D1PPRE = 4, // register values, divisor value = BIT(value - 3) = / 2
|
|
D2PPRE1 = 4,
|
|
D2PPRE2 = 4,
|
|
D3PPRE = 4
|
|
};
|
|
// PLL1_P: odd division factors are not allowed (8.7.13) (according to Cube, '1'
|
|
// is also an "odd division factor").
|
|
// Make sure your chip is revision 'V', otherwise set PLL1_N = 400
|
|
enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 480, PLL1_P = 2 };
|
|
#define FLASH_LATENCY 0x24 // WRHIGHFREQ LATENCY
|
|
#define CPU_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / D1CPRE) * 1000000)
|
|
// #define CPU_FREQUENCY ((PLL1_HSI / D1CPRE) * 1000000)
|
|
#define AHB_FREQUENCY (CPU_FREQUENCY / HPRE)
|
|
#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(D2PPRE2 - 3)))
|
|
#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(D2PPRE1 - 3)))
|
|
|
|
static inline void spin(volatile uint32_t n) {
|
|
while (n--) (void) 0;
|
|
}
|
|
|
|
struct rcc {
|
|
volatile uint32_t CR, HSICFGR, CRRCR, CSICFGR, CFGR, RESERVED1, D1CFGR,
|
|
D2CFGR, D3CFGR, RESERVED2, PLLCKSELR, PLLCFGR, PLL1DIVR, PLL1FRACR,
|
|
PLL2DIVR, PLL2FRACR, PLL3DIVR, PLL3FRACR, RESERVED3, D1CCIPR, D2CCIP1R,
|
|
D2CCIP2R, D3CCIPR, RESERVED4, CIER, CIFR, CICR, RESERVED5, BDCR, CSR,
|
|
RESERVED6, AHB3RSTR, AHB1RSTR, AHB2RSTR, AHB4RSTR, APB3RSTR, APB1LRSTR,
|
|
APB1HRSTR, APB2RSTR, APB4RSTR, GCR, RESERVED8, D3AMR, RESERVED11[9], RSR,
|
|
AHB3ENR, AHB1ENR, AHB2ENR, AHB4ENR, APB3ENR, APB1LENR, APB1HENR, APB2ENR,
|
|
APB4ENR, RESERVED12, AHB3LPENR, AHB1LPENR, AHB2LPENR, AHB4LPENR,
|
|
APB3LPENR, APB1LLPENR, APB1HLPENR, APB2LPENR, APB4LPENR, RESERVED13[4];
|
|
};
|
|
#define RCC ((struct rcc *) (0x40000000 + 0x18020000 + 0x4400))
|
|
struct pwr {
|
|
volatile uint32_t CR1, CSR1, CR2, CR3, CPUCR, RESERVED0, D3CR, RESERVED1,
|
|
WKUPCR, WKUPFR, WKUPEPR;
|
|
};
|
|
#define PWR ((struct pwr *) (0x40000000 + 0x18020000 + 0x4800))
|
|
|
|
struct nvic {
|
|
volatile uint32_t ISER[8], RESERVED0[24], ICER[8], RSERVED1[24], ISPR[8],
|
|
RESERVED2[24], ICPR[8], RESERVED3[24], IABR[8], RESERVED4[56], IP[240],
|
|
RESERVED5[644], STIR;
|
|
};
|
|
#define NVIC ((struct nvic *) 0xe000e100)
|
|
static inline void nvic_set_prio(int irq, uint32_t prio) {
|
|
NVIC->IP[irq] = prio << 4;
|
|
}
|
|
static inline void nvic_enable_irq(int irq) {
|
|
NVIC->ISER[irq >> 5] = (uint32_t) (1 << (irq & 31));
|
|
}
|
|
|
|
struct systick {
|
|
volatile uint32_t CTRL, LOAD, VAL, CALIB;
|
|
};
|
|
#define SYSTICK ((struct systick *) 0xe000e010)
|
|
static inline void systick_init(uint32_t ticks) {
|
|
if ((ticks - 1) > 0xffffff) return; // Systick timer is 24 bit
|
|
SYSTICK->LOAD = ticks - 1;
|
|
SYSTICK->VAL = 0;
|
|
SYSTICK->CTRL = BIT(0) | BIT(1) | BIT(2); // Enable systick
|
|
}
|
|
|
|
struct flash {
|
|
volatile uint32_t ACR, KEYR1, OPTKEYR, CR1, SR1, CCR1, OPTCR, OPTSR_CUR,
|
|
OPTSR_PRG, OPTCCR, PRAR_CUR1, PRAR_PRG1, SCAR_CUR1, SCAR_PRG1, WPSN_CUR1,
|
|
WPSN_PRG1, BOOT_CUR, BOOT_PRG, RESERVED0, CRCCR1, CRCSADD1, CRCEADD1,
|
|
CRCDATA, ECC_FA1, RESERVED1, KEYR2, RESERVED2, CR2, SR2, CCR2, RESERVED3,
|
|
PRAR_CUR2, PRAR_PRG2, SCAR_CUR2, SCAR_PRG2, WPSN_CUR2, WPSN_PRG2,
|
|
RESERVED4, CRCCR2, CRCSADD2, CRCEADD2, CRCDATA2, ECC_FA2;
|
|
};
|
|
#define FLASH ((struct flash *) (0x40000000UL + 0x12000000UL + 0x2000UL))
|
|
|
|
struct scb {
|
|
volatile uint32_t CPUID, ICSR, VTOR, AIRCR, SCR, CCR, SHPR[3], SHCSR, CFSR,
|
|
HFSR, DFSR, MMFAR, BFAR, AFSR, ID_PFR[2], ID_DFR, ID_AFR, ID_MFR[4],
|
|
ID_ISAR[5], RESERVED0[1], CLIDR, CTR, CCSIDR, CSSELR, CPACR,
|
|
RESERVED3[93], STIR, RESERVED4[15], MVFR0, MVFR1, MVFR2, RESERVED5[1],
|
|
ICIALLU, RESERVED6[1], ICIMVAU, DCIMVAC, DCISW, DCCMVAU, DCCMVAC, DCCSW,
|
|
DCCIMVAC, DCCISW, RESERVED7[6], ITCMCR, DTCMCR, AHBPCR, CACR, AHBSCR,
|
|
RESERVED8[1], ABFSR;
|
|
};
|
|
#define SCB ((struct scb *) 0xe000ed00)
|
|
|
|
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
|
|
enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
|
|
enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
|
|
enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
|
|
|
|
struct gpio {
|
|
volatile uint32_t MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFR[2];
|
|
};
|
|
#define GPIO(N) ((struct gpio *) (0x40000000 + 0x18020000UL + 0x400 * (N)))
|
|
|
|
static struct gpio *gpio_bank(uint16_t pin) {
|
|
return GPIO(PINBANK(pin));
|
|
}
|
|
static inline void gpio_toggle(uint16_t pin) {
|
|
struct gpio *gpio = gpio_bank(pin);
|
|
uint32_t mask = BIT(PINNO(pin));
|
|
gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
|
|
}
|
|
static inline int gpio_read(uint16_t pin) {
|
|
return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
|
|
}
|
|
static inline void gpio_write(uint16_t pin, bool val) {
|
|
struct gpio *gpio = gpio_bank(pin);
|
|
gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
|
|
}
|
|
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
|
uint8_t speed, uint8_t pull, uint8_t af) {
|
|
struct gpio *gpio = gpio_bank(pin);
|
|
uint8_t n = (uint8_t) (PINNO(pin));
|
|
RCC->AHB4ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
|
|
SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
|
|
SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
|
|
SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
|
|
SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
|
|
((uint32_t) af) << ((n & 7) * 4));
|
|
SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
|
|
}
|
|
static inline void gpio_input(uint16_t pin) {
|
|
gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
|
GPIO_PULL_NONE, 0);
|
|
}
|
|
static inline void gpio_output(uint16_t pin) {
|
|
gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
|
GPIO_PULL_NONE, 0);
|
|
}
|
|
|
|
struct syscfg {
|
|
volatile uint32_t RESERVED1, PMCR, EXTICR[4], CFGR, RESERVED2, CCCSR, CCVR,
|
|
CCCR, PWRCR, RESERVED3[61], PKGR, RESERVED4[118], UR0, UR1, UR2, UR3, UR4,
|
|
UR5, UR6, UR7, UR8, UR9, UR10, UR11, UR12, UR13, UR14, UR15, UR16, UR17;
|
|
};
|
|
#define SYSCFG ((struct syscfg *) (0x40000000UL + 0x18000000UL + 0x0400UL))
|
|
|
|
struct uart {
|
|
volatile uint32_t CR1, CR2, CR3, BRR, GTPR, RTOR, RQR, ISR, ICR, RDR, TDR,
|
|
PRESC;
|
|
};
|
|
#define UART1 ((struct uart *) 0x40011000)
|
|
#define UART2 ((struct uart *) 0x40004400)
|
|
#define UART3 ((struct uart *) 0x40004800)
|
|
#define UART_DEBUG UART1
|
|
|
|
// D2 Kernel clock (8.7.21) USART1 defaults to pclk2 (APB2), while USART2,3
|
|
// default to pclk1 (APB1). Even if using other kernel clocks, the APBx clocks
|
|
// must be enabled for CPU access, as the kernel clock drives the BRR, not the
|
|
// APB bus interface
|
|
static inline void uart_init(struct uart *uart, unsigned long baud) {
|
|
uint8_t af = 7; // Alternate function
|
|
uint16_t rx = 0, tx = 0; // pins
|
|
uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
|
|
|
|
if (uart == UART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
|
|
if (uart == UART2) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(17);
|
|
if (uart == UART3) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(18);
|
|
|
|
if (uart == UART1) tx = PIN('A', 9), rx = PIN('A', 10);
|
|
if (uart == UART2) tx = PIN('A', 2), rx = PIN('A', 3);
|
|
if (uart == UART3) tx = PIN('D', 8), rx = PIN('D', 9);
|
|
|
|
#if 0 // CONSTANT BAUD RATE FOR REMOTE DEBUGGING WHILE SETTING THE PLL
|
|
SETBITS(RCC->D2CCIP2R, 7 << 3, 3 << 3); // use HSI for UART1
|
|
freq = 64000000;
|
|
#endif
|
|
|
|
gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
|
|
gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
|
|
uart->CR1 = 0; // Disable this UART
|
|
uart->BRR = freq / baud; // Set baud rate
|
|
uart->CR1 = BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
|
|
}
|
|
static inline void uart_write_byte(struct uart *uart, uint8_t byte) {
|
|
uart->TDR = byte;
|
|
while ((uart->ISR & BIT(7)) == 0) spin(1);
|
|
}
|
|
static inline void uart_write_buf(struct uart *uart, char *buf, size_t len) {
|
|
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
|
|
}
|
|
static inline int uart_read_ready(struct uart *uart) {
|
|
return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
|
|
}
|
|
static inline uint8_t uart_read_byte(struct uart *uart) {
|
|
return (uint8_t) (uart->RDR & 255);
|
|
}
|
|
|
|
struct dbgmcu {
|
|
volatile uint32_t IDCODE, CR, RESERVED4, APB3FZ1, RESERVED5, APB1LFZ1,
|
|
RESERVED6, APB1HFZ1, RESERVED7, APB2FZ1, RESERVED8, APB4FZ1;
|
|
};
|
|
#define DBGMCU ((struct dbgmcu *) 0x5C001000UL)
|
|
|
|
static inline char chiprev(void) {
|
|
uint16_t rev = (uint16_t)(((uint32_t) DBGMCU->IDCODE) >> 16);
|
|
if (rev == 0x1003) return 'Y';
|
|
if (rev == 0x2003) return 'V';
|
|
return '?';
|
|
}
|
|
|
|
static inline unsigned int div2prescval(unsigned int div) {
|
|
// 0 --> /1; 8 --> /2 ... 11 --> /16; 12 --> /64 ... 15 --> /512
|
|
if (div == 1) return 0;
|
|
if (div > 16) div /= 2;
|
|
unsigned int val = 7;
|
|
while (div >>= 1) ++val;
|
|
return val;
|
|
}
|
|
|
|
static inline unsigned int pllrge(unsigned int f) {
|
|
unsigned int val = 0;
|
|
while (f >>= 1) ++val;
|
|
return val - 1;
|
|
}
|
|
|
|
static inline void clock_init(void) {
|
|
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
|
asm("DSB");
|
|
asm("ISB");
|
|
PWR->CR3 |= BIT(1); // select LDO (reset value)
|
|
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY
|
|
PWR->D3CR |= BIT(15) | BIT(14); // Select VOS1
|
|
uint32_t f = PWR->D3CR; // fake read to wait for bus clocking
|
|
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY
|
|
SYSCFG->PWRCR |= BIT(0); // ODEN
|
|
f = SYSCFG->PWRCR;
|
|
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY
|
|
(void) f;
|
|
SETBITS(
|
|
RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),
|
|
(div2prescval(D1CPRE) << 8) | (D1PPRE << 4) | (div2prescval(HPRE) << 0));
|
|
RCC->D2CFGR = (D2PPRE2 << 8) | (D2PPRE1 << 4);
|
|
RCC->D3CFGR = (D3PPRE << 4);
|
|
SETBITS(RCC->PLLCFGR, 3 << 2,
|
|
pllrge(PLL1_HSI / PLL1_M)
|
|
<< 2); // keep reset config (DIVP1EN, !PLL1VCOSEL), PLL1RGE
|
|
SETBITS(RCC->PLL1DIVR, (0x7F << 9) | (0x1FF << 0),
|
|
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0)); // Set PLL1_P PLL1_N
|
|
SETBITS(RCC->PLLCKSELR, 0x3F << 4,
|
|
PLL1_M << 4); // Set PLL1_M (source defaults to HSI)
|
|
RCC->CR |= BIT(24); // Enable PLL1
|
|
while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done
|
|
RCC->CFGR |= (3 << 0); // Set clock source to PLL1
|
|
while ((RCC->CFGR & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
|
|
FLASH->ACR |= FLASH_LATENCY; // default is larger
|
|
#if 0
|
|
// Enable SRAM block if you want to use it for ETH buffer (needs proper attributes in driver code)
|
|
// RCC->AHB2ENR |= BIT(29) | BIT(30) | BIT(31);
|
|
#endif
|
|
}
|