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141 lines
4.9 KiB
C
141 lines
4.9 KiB
C
// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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#pragma once
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#include <ch32v30x.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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extern uint32_t SystemCoreClock;
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extern void SystemInit(void);
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extern void SystemCoreClockUpdate(void);
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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enum {
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GPIO_MODE_INPUT,
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GPIO_MODE_OUTPUT_10M,
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GPIO_MODE_OUTPUT_2M,
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GPIO_MODE_OUTPUT_50M
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};
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enum { GPIO_OTYPE_PP, GPIO_OTYPE_OD, GPIO_OTYPE_AF_PP, GPIO_AF_OD };
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enum { GPIO_ITYPE_ANALOG, GPIO_ITYPE_FLOAT, GPIO_ITYPE_PUPD };
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#define GPIO(N) ((GPIO_TypeDef *) (GPIOA_BASE + 0x400 * (N)))
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static GPIO_TypeDef *gpio_bank(uint16_t pin) {
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return GPIO(PINBANK(pin));
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}
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static inline void gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSHR = mask << (gpio->OUTDR & mask ? 16 : 0);
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}
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static inline bool gpio_read(uint16_t pin) {
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return gpio_bank(pin)->INDR & BIT(PINNO(pin)) ? true : false;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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gpio->BSHR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t cfg) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t bank = (uint8_t) PINBANK(pin), no = (uint8_t) PINNO(pin);
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RCC->APB2PCENR |= BIT(bank + 2); // Enable GPIO clock, section 3.4.7
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if (mode != GPIO_MODE_INPUT && cfg == GPIO_OTYPE_AF_PP) {
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RCC->APB2PCENR |= BIT(0); // Enable AFIO
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}
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volatile uint32_t *r = &gpio->CFGLR;
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if (no > 7) r = &gpio->CFGHR, no -= 8;
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uint8_t v = (mode & 3U) | ((cfg & 3U) << 2);
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CLRSET(*r, 15U << (no * 4), v << (no * 4));
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_ITYPE_PUPD);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT_50M, GPIO_OTYPE_PP);
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}
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static inline void uart_init(USART_TypeDef *uart, unsigned baud) {
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uint16_t rx = 0, tx = 0; // pins
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uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
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if (uart == USART1) freq = SystemCoreClock, RCC->APB2PCENR |= BIT(14);
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if (uart == USART2) freq = SystemCoreClock, RCC->APB1PCENR |= BIT(17);
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if (uart == USART3) freq = SystemCoreClock, RCC->APB1PCENR |= BIT(18);
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if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
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// if (uart == USART1) tx = PIN('B', 6), rx = PIN('B', 7);
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if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
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if (uart == USART3) tx = PIN('B', 10), rx = PIN('B', 11);
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gpio_init(tx, GPIO_MODE_OUTPUT_50M, GPIO_OTYPE_AF_PP);
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gpio_init(rx, GPIO_MODE_INPUT, GPIO_ITYPE_PUPD);
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uart->CTLR1 = 0; // Disable this UART
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unsigned div = freq / baud * 100 / 16; // 18.3
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uart->BRR = (uint16_t) (((div / 100) << 4) | (div * 16 / 100));
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uart->CTLR1 = BIT(13) | BIT(2) | BIT(3); // Set UE, RE, TE
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}
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static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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uart->DATAR = byte;
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volatile int timeout = 999;
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while ((uart->STATR & BIT(7)) == 0 && timeout--) spin(1);
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}
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static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(USART_TypeDef *uart) {
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return uart->STATR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->DATAR & 255U);
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}
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static inline void ethernet_init(void) {
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// Set 60MHz ethernet clock
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RCC->CTLR &= ~BIT(28); // PLL3 off
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CLRSET(RCC->CFGR2, 15U << 4, 1U << 4); // 3.4.12: PREDIV2 = 2
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CLRSET(RCC->CFGR2, 15U << 12, 13U << 12); // 3.4.12: PLL3MUL = 15
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RCC->CTLR |= BIT(28); // PLL3 on
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EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN; // Enable built-in 10M PHY
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#if 0
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// RMII mode
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// 27.1.3 : init pins
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uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),
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PIN('B', 11), PIN('B', 12), PIN('B', 13),
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PIN('C', 1), PIN('C', 4), PIN('C', 5)};
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for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
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gpio_init(pins[i], GPIO_MODE_OUTPUT_50M, GPIO_OTYPE_AF_PP);
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}
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AFIO->PCFR1 |= BIT(23); // Use RMII
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#endif
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RCC->AHBPCENR |= BIT(14) | BIT(15) | BIT(16); // Enable MAC, TX, RX
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NVIC_EnableIRQ(ETH_IRQn);
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// NVIC_SetPriority(ETH_IRQn, 0);
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}
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static inline void rng_init(void) {
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RNG->CR |= RNG_CR_RNGEN;
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}
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static inline uint32_t rng_read(void) {
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return RNG->DR;
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}
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// Helper macro for MAC generation
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#define ROM_MAC ((uint8_t *) (0X1ffff7e8 + 5))
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ 2, ROM_MAC[0], ROM_MAC[1], ROM_MAC[2], ROM_MAC[3], ROM_MAC[4] }
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