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46 lines
1.8 KiB
C
46 lines
1.8 KiB
C
// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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//
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// This file contains essentials required by the CMSIS:
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// uint32_t SystemCoreClock - holds the system core clock value
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// SystemInit() - initialises the system, e.g. sets up clocks
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#include "hal.h"
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uint32_t SystemCoreClock = CPU_FREQUENCY;
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void SystemInit(void) { // Called automatically by startup code
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SCB->CPACR |= ((3UL << 20U) | (3UL << 22U)); // Enable FPU
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asm("DSB");
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asm("ISB");
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// Set flash latency. RM0481, section 7.11.1, section 7.3.4 table 37
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SETBITS(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
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FLASH_ACR_LATENCY_5WS | FLASH_ACR_WRHIGHFREQ_1);
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if (ldo_is_on()) {
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PWR->VOSCR = PWR_VOSCR_VOS_0 | PWR_VOSCR_VOS_1; // Select VOS0
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} else {
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PWR->VOSCR = PWR_VOSCR_VOS_1; // Select VOS1
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}
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uint32_t f = PWR->VOSCR; // fake read to wait for bus clocking
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while ((PWR->VOSSR & PWR_VOSSR_ACTVOSRDY) == 0) spin(1);
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(void) f;
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RCC->CR = RCC_CR_HSION; // Clear HSI clock divisor
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while ((RCC->CR & RCC_CR_HSIRDY) == 0) spin(1); // Wait until done
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RCC->CFGR2 = (PPRE3 << 12) | (PPRE2 << 8) | (PPRE1 << 4) | (HPRE << 0);
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RCC->PLL1DIVR =
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((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0); // Set PLL1_P PLL1_N
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// Enable P and Q divider outputs; set PLL1_M, select HSI as source,
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// !PLL1VCOSEL, PLL1RGE=0
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RCC->PLL1CFGR =
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RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1PEN | (PLL1_M << 8) | (1 << 0);
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RCC->CR |= RCC_CR_PLL1ON; // Enable PLL1
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while ((RCC->CR & RCC_CR_PLL1RDY) == 0) spin(1); // Wait until done
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RCC->CFGR1 |= (3 << 0); // Set clock source to PLL1
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while ((RCC->CFGR1 & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
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rng_init(); // Initialise random number generator
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// let FreeRTOS initialize SysTick
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}
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