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357 lines
17 KiB
C
357 lines
17 KiB
C
// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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// https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMXRT1060XRM.pdf
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// https://cache.nxp.com/secured/assets/documents/en/user-guide/MIMXRT1060EVKBUM.pdf
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#pragma once
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#include "MIMXRT1062.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - '0') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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// Use LED for blinking, D8: GPIO_AD_B0_08. GPIO1.8 (schematics, RM)
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#define LED PIN('1', 8)
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#ifndef UART_DEBUG
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#define UART_DEBUG LPUART1
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#endif
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// No settable constants, see sysinit.c
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#define SYS_FREQUENCY 600000000UL
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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enum { CLOCK_OFF = 0U, CLOCK_ON_RUN = 1U, CLOCK_ON_RUN_WAIT = 3U };
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static inline void clock_periph(uint32_t index, uint32_t shift, uint32_t val) {
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volatile uint32_t *r = &CCM->CCGR0;
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SETBITS(r[index], 3UL << shift, val << shift);
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}
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// which peripheral feeds the pin
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static inline void gpio_mux_config(uint16_t index, uint8_t af) {
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IOMUXC->SW_MUX_CTL_PAD[index] = af;
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}
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// which pin feeds the peripheral (2nd stage)
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static inline void periph_mux_config(uint16_t index, uint8_t in) {
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IOMUXC->SELECT_INPUT[index] = in;
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}
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH };
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enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP };
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static inline GPIO_Type *gpio_bank(uint16_t pin) {
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static const GPIO_Type *g[] = {NULL, GPIO1, GPIO2, GPIO3, NULL, GPIO5};
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return (GPIO_Type *) g[PINBANK(pin)];
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}
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// pin driver/pull-up/down configuration (ignore "keeper")
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static inline void gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed,
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uint8_t pull) {
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bool dopull = pull > 0;
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if (dopull) --pull;
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IOMUXC->SW_PAD_CTL_PAD[index] =
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_ODE(type) |
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IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH) |
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IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PKE(dopull) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(pull) | IOMUXC_SW_PAD_CTL_PAD_DSE(7);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull) {
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GPIO_Type *gpio = gpio_bank(pin);
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uint8_t bit = (uint8_t) PINNO(pin);
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uint32_t mask = (uint32_t) BIT(PINNO(pin));
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clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s
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switch (PINBANK(pin)) {
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case 1:
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 + bit, 5);
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 + bit, type, speed,
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pull);
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clock_periph(1, CCM_CCGR1_CG13_SHIFT, CLOCK_ON_RUN_WAIT);
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break;
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case 2:
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 + bit, 5);
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 + bit, type, speed,
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pull);
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clock_periph(0, CCM_CCGR0_CG15_SHIFT, CLOCK_ON_RUN_WAIT);
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break;
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case 3:
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gpio_mux_config(bit < 12 ? kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 + bit
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: bit < 18
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? kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 + bit - 12
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: kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 + bit - 18,
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5);
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gpio_pad_config(bit < 12 ? kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 + bit
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: bit < 18
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? kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 + bit - 12
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: kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 + bit - 18,
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type, speed, pull);
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clock_periph(2, CCM_CCGR2_CG13_SHIFT, CLOCK_ON_RUN_WAIT);
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break;
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case 5:
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// TODO(): support sw_mux
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clock_periph(1, CCM_CCGR1_CG15_SHIFT, CLOCK_ON_RUN_WAIT);
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break;
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default:
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break;
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}
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gpio->IMR &= ~mask;
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if (mode == GPIO_MODE_INPUT) {
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gpio->GDIR &= ~mask;
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} else {
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gpio->GDIR |= mask;
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}
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
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GPIO_PULL_NONE);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
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GPIO_PULL_NONE);
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}
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static inline bool gpio_read(uint16_t pin) {
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GPIO_Type *gpio = gpio_bank(pin);
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uint32_t mask = (uint32_t) BIT(PINNO(pin));
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return gpio->DR & mask;
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}
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static inline void gpio_write(uint16_t pin, bool value) {
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GPIO_Type *gpio = gpio_bank(pin);
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uint32_t mask = (uint32_t) BIT(PINNO(pin));
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if (value) {
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gpio->DR |= mask;
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} else {
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gpio->DR &= ~mask;
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}
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}
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static inline void gpio_toggle(uint16_t pin) {
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gpio_write(pin, !gpio_read(pin));
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}
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// 14.5 Table 14-4: uart_clk_root
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// see sysinit.c for clocks, (14.7.9: defaults to pll3_80m = PLL3/6/1 = 80MHz)
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static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
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uint8_t af = 2; // Alternate function
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uint16_t mr = 0, pr = 0, mt = 0, pt = 0; // pins
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uint32_t freq = 80000000; // uart_clk_root frequency
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if (uart == LPUART1)
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mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12,
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pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12,
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mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13,
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pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13;
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if (uart == LPUART3)
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mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06,
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pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06,
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mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07,
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pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07;
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if (uart == LPUART1) clock_periph(5, CCM_CCGR5_CG12_SHIFT, CLOCK_ON_RUN_WAIT);
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if (uart == LPUART3) clock_periph(0, CCM_CCGR0_CG6_SHIFT, CLOCK_ON_RUN_WAIT);
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clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s
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gpio_mux_config(mt, af);
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gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
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gpio_mux_config(mr, af);
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gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
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uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
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uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
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SETBITS(uart->BAUD,
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LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK,
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LPUART_BAUD_OSR(16 - 1) |
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LPUART_BAUD_SBR(freq / (16 * baud))); // Rx sample at 16x
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SETBITS(uart->CTRL,
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LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
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LPUART_CTRL_IDLECFG_MASK,
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LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) |
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LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit
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uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
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}
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static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
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uart->DATA = byte;
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while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
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}
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static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(LPUART_Type *uart) {
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(void) uart;
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return uart->STAT & LPUART_STAT_RDRF_MASK;
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}
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static inline uint8_t uart_read_byte(LPUART_Type *uart) {
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return (uint8_t) (uart->DATA & 255);
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}
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static inline void rng_init(void) {
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clock_periph(6, CCM_CCGR6_CG6_SHIFT, CLOCK_ON_RUN_WAIT); // trng_clk
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SETBITS(TRNG->MCTL,
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TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK | TRNG_MCTL_RST_DEF_MASK,
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TRNG_MCTL_PRGM(1) | TRNG_MCTL_ERR(1) |
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TRNG_MCTL_RST_DEF(1)); // reset to default values
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SETBITS(TRNG->MCTL, TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK,
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TRNG_MCTL_PRGM(0)); // set to run mode
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(void) TRNG->ENT[TRNG_ENT_COUNT - 1]; // start new entropy generation
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(void) TRNG->ENT[0]; // defect workaround
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}
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static inline uint32_t rng_read(void) {
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static uint8_t idx = 0;
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while ((TRNG->MCTL & TRNG_MCTL_ENT_VAL_MASK) == 0) (void) 0;
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uint32_t data = TRNG->ENT[idx++]; // read data
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idx %= TRNG_ENT_COUNT; // stay within array limits
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if (idx == 0) // we've just read TRNG_ENT_COUNT - 1
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(void) TRNG->ENT[0]; // defect workaround
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return data;
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}
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// - PHY has no xtal, XI driven from ENET_REF_CLK1 (labeled as ENET_TX_REF_CLK
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// (GPIO_AD_B1_10)), generated by the MCU
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// - PHY RST connected to GPIO1.9 (GPIO_AD_B0_09); INTRP/NAND_TREE connected to
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// GPIO1.10 (GPIO_AD_B0_10)
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// - 41.4 REF_CLK1 is RMII mode reference clock for Rx, Tx, and SMI; it is I/O
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// - 11.3.2 IOMUXC_GPR_GPR1
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// - bit 13: ENET1_CLK_SEL --> 0 ENET1 TX reference clock driven by
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// ref_enetpll and output via ENET_REF_CLK1 (labeled as ENET_REF_CLK
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// elsewhere)
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// - bit 17: ENET1_TX_CLK_DIR --> 1 ENET1_TX_CLK output driver enabled
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// - 14.6.1.3.6 Ethernet PLL (PLL6)
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// - 14.8.14: configure PLL6 to generate 50MHz clocks for ENET and RMII.
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static inline void ethernet_init(void) {
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// setup PLL and clock ENET from it
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SETBITS(CCM_ANALOG->PLL_ENET, CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK,
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CCM_ANALOG_PLL_ENET_BYPASS_MASK |
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CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(0)); // bypass to 24MHz osc
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SETBITS(
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CCM_ANALOG->PLL_ENET,
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CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK,
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CCM_ANALOG_PLL_ENET_DIV_SELECT(1) | CCM_ANALOG_PLL_ENET_ENABLE_MASK);
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while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
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spin(1); // wait until it is stable
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CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK;
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gpio_init(PIN('1', 9), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_MEDIUM, GPIO_PULL_UP); // set GPIO1.9 as GPIO (PHY \RST)
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gpio_write(PIN('1', 9), 0); // reset PHY
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10,
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6); // set for ENET_REF_CLK
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IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10] |=
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IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
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periph_mux_config(kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT,
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1); // drive peripheral from B1_10, so RMII clock is taken
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// from ENET_REF_CLK
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_UP);
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IOMUXC_GPR->GPR1 |=
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IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(1); // Set ENET_TX_CLK as output
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04, 3); // set for RXDATA0
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periph_mux_config(kIOMUXC_ENET0_RXDATA_SELECT_INPUT,
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1); // drive peripheral from B1_04
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_UP);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05, 3); // set for RXDATA1
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periph_mux_config(kIOMUXC_ENET1_RXDATA_SELECT_INPUT,
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1); // drive peripheral from B1_05
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_UP);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06, 3); // set for CRS
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periph_mux_config(kIOMUXC_ENET_RXEN_SELECT_INPUT,
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1); // drive peripheral from B1_06
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_UP);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07, 3); // set for TXDATA0
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_UP);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08, 3); // set for TXDATA1
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_UP);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09, 3); // set for TXEN
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_UP);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11, 3); // set for RXERR
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periph_mux_config(kIOMUXC_ENET_RXERR_SELECT_INPUT,
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1); // drive peripheral from B1_11
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, GPIO_PULL_UP);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, 4); // set for MDC
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, 4); // set for MDIO
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periph_mux_config(kIOMUXC_ENET_MDIO_SELECT_INPUT,
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1); // drive peripheral from EMC_41
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
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gpio_init(PIN('1', 10), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_MEDIUM,
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GPIO_PULL_UP); // set GPIO1.10 as GPIO (PHY INTRP/NAND_TREE)
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gpio_write(PIN('1', 10), 1); // prevent NAND_TREE
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spin(10000); // keep PHY RST low for a while
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gpio_write(PIN('1', 9), 1); // deassert RST
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gpio_init(PIN('1', 10), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM,
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GPIO_PULL_UP); // setup IRQ (pulled-up)(not used)
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clock_periph(1, CCM_CCGR1_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enet_ipg_clk
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NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler
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}
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// Helper macro for MAC generation, byte reads not allowed
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ \
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2, OCOTP->CFG0 & 255, (OCOTP->CFG0 >> 10) & 255, \
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((OCOTP->CFG0 >> 19) ^ (OCOTP->CFG1 >> 19)) & 255, \
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(OCOTP->CFG1 >> 10) & 255, OCOTP->CFG1 & 255 \
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}
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// NOTE: You can fuse your own MAC and read it from OCOTP->MAC0, OCOTP->MAC1,
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// OCOTP->MAC2
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static inline void flash_init(void) { // QSPI in FlexSPI
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// set pins
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clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05, 1); // set for DQS
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IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
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periph_mux_config(kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT, 0); // drive peripheral from B1_05
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06, 1); // set for SS
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IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07, 1); // set for SCLK
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IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
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periph_mux_config(kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT, 0); // drive peripheral from B1_07
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08, 1); // set for DATA0
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IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
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periph_mux_config(kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT, 0); // drive peripheral from B1_08
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09, 1); // set for DATA1
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IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
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periph_mux_config(kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT, 0); // drive peripheral from B1_09
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10, 1); // set for DATA2
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IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
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periph_mux_config(kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT, 0); // drive peripheral from B1_10
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11, 1); // set for DATA3
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IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
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periph_mux_config(kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT, 0); // drive peripheral from B1_11
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gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
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// set FlexSPI clock
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SETBITS(CCM->CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK | CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_CSCMR1_FLEXSPI_CLK_SEL(3) | CCM_CSCMR1_FLEXSPI_PODF(7)); // select PLL3 PFD0 /8
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clock_periph(6, CCM_CCGR6_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enable
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}
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