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https://github.com/cesanta/mongoose.git
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220 lines
8.3 KiB
C
220 lines
8.3 KiB
C
// Copyright (c) 2022 Cesanta Software Limited
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// SPDX-License-Identifier: MIT
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//
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// https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/DataSheets/SAM-D5x-E5x-Family-Data-Sheet-DS60001507.pdf
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// https://ww1.microchip.com/downloads/en/DeviceDoc/70005321A.pdf
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#ifndef LED_PIN
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#define LED_PIN PIN('C', 18)
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#endif
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#ifndef BUTTON_PIN
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#define BUTTON_PIN PIN('B', 31)
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#endif
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#ifndef UART_DEBUG
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#define UART_DEBUG USART1
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#endif
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#pragma once
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#include <sam.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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static inline uint32_t clock_sys_freq(void) {
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return 48000000U;
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}
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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#define GPIO(N) ((port_group_registers_t *) (PORT_BASE_ADDRESS + 0x80 * (N)))
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typedef port_group_registers_t GPIO_TypeDef;
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static inline GPIO_TypeDef *gpio_bank(uint16_t pin) {
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return GPIO(PINBANK(pin));
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}
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static inline void gpio_toggle(uint16_t pin) {
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gpio_bank(pin)->PORT_OUTTGL = BIT(PINNO(pin));
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}
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static inline bool gpio_read(uint16_t pin) {
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return gpio_bank(pin)->PORT_IN & BIT(PINNO(pin));
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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if (val) {
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gpio->PORT_OUTSET = BIT(PINNO(pin));
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} else {
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gpio->PORT_OUTCLR = BIT(PINNO(pin));
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}
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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(void) type, (void) speed, (void) pull, (void) af;
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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MCLK_REGS->MCLK_APBBMASK |= MCLK_APBBMASK_PORT_Msk;
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if (mode == GPIO_MODE_INPUT) {
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gpio->PORT_DIRCLR = mask;
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} else {
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gpio->PORT_DIRSET = mask;
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}
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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typedef sercom_usart_int_registers_t USART_TypeDef;
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#define USART1 ((USART_TypeDef *) SERCOM0_BASE_ADDRESS)
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#define USART2 ((USART_TypeDef *) SERCOM1_BASE_ADDRESS)
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#define USART3 ((USART_TypeDef *) SERCOM2_BASE_ADDRESS)
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static inline bool uart_init(USART_TypeDef *uart, unsigned long baud) {
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uint16_t rx = 0, tx = 0; // Pins
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uint8_t rx_mux = 0, tx_mux = 0;
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if (uart == USART1) {
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MCLK_REGS->MCLK_APBAMASK |= MCLK_APBAMASK_SERCOM0_Msk;
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GCLK_REGS->GCLK_PCHCTRL[SERCOM0_GCLK_ID_CORE] =
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GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN_Msk;
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GCLK_REGS->GCLK_PCHCTRL[SERCOM0_GCLK_ID_SLOW] =
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GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN_Msk;
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tx = PIN('A', 4), rx = PIN('A', 5);
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rx_mux = MUX_PA05D_SERCOM0_PAD1, tx_mux = MUX_PA04D_SERCOM0_PAD0;
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} else if (uart == USART2) {
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MCLK_REGS->MCLK_APBAMASK |= MCLK_APBAMASK_SERCOM1_Msk;
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tx = PIN('C', 27), rx = PIN('C', 28);
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} else if (uart == USART3) {
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MCLK_REGS->MCLK_APBBMASK |= MCLK_APBBMASK_SERCOM2_Msk;
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tx = PIN('A', 9), rx = PIN('A', 8);
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} else {
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return false;
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}
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gpio_bank(rx)->PORT_WRCONFIG =
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PORT_WRCONFIG_PMUX(rx_mux) | PORT_WRCONFIG_WRPMUX(1) |
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PORT_WRCONFIG_PMUXEN(1) | PORT_WRCONFIG_WRPINCFG(1) | BIT(PINNO(rx));
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gpio_bank(tx)->PORT_WRCONFIG =
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PORT_WRCONFIG_PMUX(tx_mux) | PORT_WRCONFIG_WRPMUX(1) |
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PORT_WRCONFIG_PMUXEN(1) | PORT_WRCONFIG_WRPINCFG(1) | BIT(PINNO(tx));
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uart->SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_DORD(1) |
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SERCOM_USART_INT_CTRLA_MODE(1 /* INT_CLK */) |
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SERCOM_USART_INT_CTRLA_RXPO(1 /* PAD1 */) |
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SERCOM_USART_INT_CTRLA_TXPO(0 /* PAD0 */) |
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SERCOM_USART_INT_CTRLA_SAMPR(1);
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uart->SERCOM_BAUD = (uint16_t) (clock_sys_freq() / (16 * baud));
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uart->SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_RXEN(1) |
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SERCOM_USART_INT_CTRLB_TXEN(1) |
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SERCOM_USART_INT_CTRLB_CHSIZE(0);
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while (uart->SERCOM_SYNCBUSY & SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk) spin(1);
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uart->SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE(1);
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while (uart->SERCOM_SYNCBUSY & SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk) spin(1);
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return true;
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}
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static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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while (!(uart->SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk)) spin(1);
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uart->SERCOM_DATA = byte;
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}
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static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline bool uart_read_ready(USART_TypeDef *uart) {
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return (uart->SERCOM_INTFLAG & SERCOM_USART_EXT_INTFLAG_RXC_Msk);
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}
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static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->SERCOM_DATA & 255U);
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}
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static inline void rng_init(void) {
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MCLK_REGS->MCLK_APBCMASK |= MCLK_APBCMASK_TRNG_Msk;
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TRNG_REGS->TRNG_CTRLA = TRNG_CTRLA_ENABLE_Msk;
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}
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static inline uint32_t rng_read(void) {
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while ((TRNG_REGS->TRNG_INTFLAG & TRNG_INTFLAG_DATARDY_Msk) == 0) spin(1);
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return TRNG_REGS->TRNG_DATA;
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}
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#define UID_BASE_W0 0x008061FC // Word 0 location of the 128-bit chip ID
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#define UID_BASE_W1_3 0x00806010 // Words 1-3 location of the 128-bit chip ID
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#define UUID(n) ((n >= 0 && n <= 3) ? \
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(((uint8_t *) UID_BASE_W0)[n]) : \
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(((uint8_t *) UID_BASE_W1_3)[n - 4]))
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ \
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2, UUID(0) ^ UUID(1) ^ UUID(2), UUID(3) ^ UUID(4) ^ UUID(5), \
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UUID(6) ^ UUID(7) ^ UUID(8), UUID(9) ^ UUID(10) ^ UUID(11), \
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UUID(12) ^ UUID(13) ^ UUID(14) ^ UUID(15) \
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}
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static inline bool timer_expired(volatile uint64_t *t, uint64_t prd,
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uint64_t now) {
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if (now + prd < *t) *t = 0; // Time wrapped? Reset timer
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if (*t == 0) *t = now + prd; // Firt poll? Set expiration
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if (*t > now) return false; // Not expired yet, return
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*t = (now - *t) > prd ? now + prd : *t + prd; // Next expiration time
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return true; // Expired, return true
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}
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static inline void clock_init(void) {
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SCB->CPACR |= (15U << 20); // Enable FPU
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SysTick_Config(clock_sys_freq() / 1000); // Sys tick every 1ms
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}
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static inline void gpio_set_irq_handler(uint16_t pin, void (*fn)(void *),
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void *arg) {
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(void) pin, (void) fn, (void) arg;
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}
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static inline void ethernet_init(void) {
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uint16_t pins[] = {PIN('A', 12), PIN('A', 13), PIN('A', 14), PIN('A', 15),
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PIN('A', 17), PIN('A', 18), PIN('A', 19), PIN('C', 11),
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PIN('C', 12), PIN('C', 20)};
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uint32_t af[] = {MUX_PA12L_GMAC_GRX1, MUX_PA13L_GMAC_GRX0,
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MUX_PA14L_GMAC_GTXCK, MUX_PA15L_GMAC_GRXER,
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MUX_PA17L_GMAC_GTXEN, MUX_PA18L_GMAC_GTX0,
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MUX_PA19L_GMAC_GTX1, MUX_PC11L_GMAC_GMDC,
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MUX_PC12L_GMAC_GMDIO, MUX_PC20L_GMAC_GRXDV};
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MCLK_REGS->MCLK_APBBMASK |= MCLK_APBBMASK_PORT_Msk;
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for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
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int bank = PINBANK(pins[i]), no = PINNO(pins[i]);
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PORT_REGS->GROUP[bank].PORT_PINCFG[no] |= PORT_PINCFG_PMUXEN_Msk;
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volatile uint8_t *m = &PORT_REGS->GROUP[bank].PORT_PMUX[no / 2], v = m[0];
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if (no & 1) {
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m[0] = (uint8_t) ((v & ~0xf0) | PORT_PMUX_PMUXO(af[i]));
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} else {
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m[0] = (uint8_t) ((v & ~0x0f) | PORT_PMUX_PMUXE(af[i]));
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}
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}
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PORT_REGS->GROUP[0].PORT_PINCFG[17] |= PORT_PINCFG_DRVSTR_Msk;
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PORT_REGS->GROUP[0].PORT_PINCFG[18] |= PORT_PINCFG_DRVSTR_Msk;
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PORT_REGS->GROUP[0].PORT_PINCFG[19] |= PORT_PINCFG_DRVSTR_Msk;
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// Reset PHY
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uint16_t phy_pin = PIN('C', 21);
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gpio_output(phy_pin);
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gpio_write(phy_pin, false);
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spin(999);
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gpio_write(phy_pin, true);
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spin(999);
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}
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