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176 lines
6.2 KiB
C
176 lines
6.2 KiB
C
// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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// https://www.ti.com/lit/pdf/spms433
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#pragma once
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#include "TM4C1294NCPDT.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((bank << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) pinbank(pin >> 8)
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// This MCU doesn't have GPIOI nor GPIOO
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static inline unsigned int pinbank(unsigned int bank) {
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bank = bank > 'O' ? bank - 2 : bank > 'I' ? bank - 1 : bank;
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return bank - 'A';
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}
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// 5.5, Table 5-12: configure flash (and EEPROM) timing in accordance to clock
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// freq
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enum {
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PLL_CLK = 25,
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PLL_M = 96,
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PLL_N = 5,
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PLL_Q = 1,
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PSYSDIV = 4
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}; // Run at 120 Mhz
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#define PLL_FREQ (PLL_CLK * PLL_M / PLL_N / PLL_Q / PSYSDIV)
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#define FLASH_CLKHIGH 6
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#define FLASH_WAITST 5
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#define SYS_FREQUENCY (PLL_FREQ * 1000000)
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_HIGH };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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#define GPIO(bank) ((GPIOA_AHB_Type *) (GPIOA_AHB_BASE + 0x1000U * (bank)))
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// CMSIS header forces 0xFF mask when writing to DATA (see 10.6 in datasheet)
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// and does not seem to support that feature for writing by defining RESERVED0
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// to read-only
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static inline void gpio_toggle(uint16_t pin) {
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GPIOA_AHB_Type *gpio = GPIO(PINBANK(pin));
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volatile uint32_t *GPIODATA = (volatile uint32_t *) gpio->RESERVED0;
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uint8_t mask = BIT(PINNO(pin));
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GPIODATA[mask] ^= mask;
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}
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static inline int gpio_read(uint16_t pin) {
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GPIOA_AHB_Type *gpio = GPIO(PINBANK(pin));
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volatile uint32_t *GPIODATA = (volatile uint32_t *) gpio->RESERVED0;
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uint8_t mask = BIT(PINNO(pin));
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return GPIODATA[mask] ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIOA_AHB_Type *gpio = GPIO(PINBANK(pin));
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volatile uint32_t *GPIODATA = (volatile uint32_t *) gpio->RESERVED0;
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uint8_t mask = BIT(PINNO(pin));
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GPIODATA[mask] = val ? mask : 0;
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIOA_AHB_Type *gpio = GPIO(PINBANK(pin));
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uint8_t n = (uint8_t) (PINNO(pin));
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SYSCTL->RCGCGPIO |= BIT(PINBANK(pin)); // Enable GPIO clock
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if (mode == GPIO_MODE_ANALOG) {
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gpio->AMSEL |= BIT(PINNO(pin));
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return;
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}
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if (mode == GPIO_MODE_INPUT) {
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gpio->DIR &= ~BIT(PINNO(pin));
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} else if (mode == GPIO_MODE_OUTPUT) {
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gpio->DIR |= BIT(PINNO(pin));
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} else { // GPIO_MODE_AF
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SETBITS(gpio->PCTL, 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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gpio->AFSEL |= BIT(PINNO(pin));
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}
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gpio->DEN |= BIT(PINNO(pin)); // Enable pin as digital function
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if (type == GPIO_OTYPE_OPEN_DRAIN)
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gpio->ODR |= BIT(PINNO(pin));
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else // GPIO_OTYPE_PUSH_PULL
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gpio->ODR &= ~BIT(PINNO(pin));
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if (speed == GPIO_SPEED_LOW)
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gpio->SLR |= BIT(PINNO(pin));
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else // GPIO_SPEED_HIGH
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gpio->SLR &= ~BIT(PINNO(pin));
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if (pull == GPIO_PULL_UP) {
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gpio->PUR |= BIT(PINNO(pin)); // setting one...
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} else if (pull == GPIO_PULL_DOWN) {
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gpio->PDR |= BIT(PINNO(pin)); // ...just clears the other
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} else {
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gpio->PUR &= ~BIT(PINNO(pin));
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gpio->PDR &= ~BIT(PINNO(pin));
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}
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_irq_attach(uint16_t pin) {
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uint8_t irqvecs[] = {16, 17, 18, 19, 20, 30, 31, 32,
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51, 52, 53, 72, 73, 76, 84};
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GPIOA_AHB_Type *gpio = GPIO(PINBANK(pin));
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gpio->IS &= ~BIT(PINNO(pin)); // edge sensitive
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gpio->IBE |= BIT(PINNO(pin)); // both edges
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gpio->IM |= BIT(PINNO(pin)); // enable pin irq
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int irqvec = irqvecs[PINBANK(pin)]; // IRQ vector index, 2.5.2
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NVIC_SetPriority(irqvec, 3);
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NVIC_EnableIRQ(irqvec);
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}
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#ifndef UART_DEBUG
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#define UART_DEBUG UART0
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#endif
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#define UART_OFFSET 0x1000
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#define UART(N) ((UART0_Type *) (UART0_BASE + UART_OFFSET * (N)))
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#define UARTNO(u) ((uint8_t) (((unsigned int) (u) -UART0_BASE) / UART_OFFSET))
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static inline void uart_init(UART0_Type *uart, unsigned long baud) {
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struct uarthw {
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uint16_t rx, tx; // pins
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uint8_t af; // Alternate function
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};
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// rx, tx, af for UART0,1,2
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struct uarthw uarthw[3] = {{PIN('A', 0), PIN('A', 1), 1},
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{PIN('B', 0), PIN('B', 1), 1},
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{PIN('A', 6), PIN('A', 7), 1}}; // or PD4, PD5...
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uint8_t uartno = UARTNO(uart);
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SYSCTL->RCGCUART |= BIT(uartno); // Enable peripheral clock
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gpio_init(uarthw[uartno].tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, 0, uarthw[uartno].af);
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gpio_init(uarthw[uartno].rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, 0, uarthw[uartno].af);
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// (16.3.2) ClkDiv = 16 (HSE=0)
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// BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
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// UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
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// must write in this order
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uart->CTL = 0; // Disable this UART, clear HSE
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uart->IBRD = SYS_FREQUENCY / (16 * baud); // Baud rate, integer part
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uart->FBRD = ((SYS_FREQUENCY % (16 * baud)) >> 26) &
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0x3F; // Baud rate, fractional part
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uart->LCRH = (3 << 5); // 8N1, no FIFOs;
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uart->CTL |= BIT(0) | BIT(9) | BIT(8); // Set UARTEN, RXE, TXE
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}
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static inline void uart_write_byte(UART0_Type *uart, uint8_t byte) {
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uart->DR = byte;
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while ((uart->FR & BIT(7)) == 0) spin(1);
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}
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static inline void uart_write_buf(UART0_Type *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(UART0_Type *uart) {
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return uart->FR & BIT(6); // If RXFF bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(UART0_Type *uart) {
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return (uint8_t) (uart->DR & 0xFF);
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}
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