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https://github.com/cesanta/mongoose.git
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306 lines
12 KiB
C
306 lines
12 KiB
C
#pragma once
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#define HAL_ETH_MODULE_ENABLED
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#define HAL_RCC_MODULE_ENABLED
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#define HAL_CORTEX_MODULE_ENABLED
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#define HAL_GPIO_MODULE_ENABLED
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#include "stm32f7xx.h"
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#include "stm32f7xx_hal_cortex.h"
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#include "stm32f7xx_hal_def.h"
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#include "stm32f7xx_hal_rcc.h"
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#include "stm32f7xx_hal_gpio.h"
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#define UID_BASE 0x1FF0F420UL
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#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
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#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
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#define assert_param(expr) ((void) 0U)
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#define HAL_MODULE_ENABLED
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#define HAL_ADC_MODULE_ENABLED
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#define HAL_CAN_MODULE_ENABLED
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#define HAL_CEC_MODULE_ENABLED
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#define HAL_CRC_MODULE_ENABLED
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#define HAL_CRYP_MODULE_ENABLED
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#define HAL_DAC_MODULE_ENABLED
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#define HAL_DCMI_MODULE_ENABLED
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#define HAL_DMA_MODULE_ENABLED
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#define HAL_DMA2D_MODULE_ENABLED
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#define HAL_ETH_MODULE_ENABLED
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#define HAL_FLASH_MODULE_ENABLED
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//#define HAL_NAND_MODULE_ENABLED
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#define HAL_NOR_MODULE_ENABLED
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#define HAL_SRAM_MODULE_ENABLED
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#define HAL_SDRAM_MODULE_ENABLED
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#define HAL_HASH_MODULE_ENABLED
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#define HAL_GPIO_MODULE_ENABLED
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#define HAL_I2C_MODULE_ENABLED
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//#define HAL_I2S_MODULE_ENABLED
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//#define HAL_IWDG_MODULE_ENABLED
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#define HAL_LPTIM_MODULE_ENABLED
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#define HAL_LTDC_MODULE_ENABLED
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#define HAL_PWR_MODULE_ENABLED
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#define HAL_QSPI_MODULE_ENABLED
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#define HAL_RCC_MODULE_ENABLED
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#define HAL_RNG_MODULE_ENABLED
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#define HAL_RTC_MODULE_ENABLED
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//#define HAL_SAI_MODULE_ENABLED
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#define HAL_SD_MODULE_ENABLED
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#define HAL_SPI_MODULE_ENABLED
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#define HAL_TIM_MODULE_ENABLED
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#define HAL_UART_MODULE_ENABLED
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#define HAL_USART_MODULE_ENABLED
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#define HAL_IRDA_MODULE_ENABLED
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#define HAL_SMARTCARD_MODULE_ENABLED
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//#define HAL_WWDG_MODULE_ENABLED
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#define HAL_CORTEX_MODULE_ENABLED
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//#define HAL_PCD_MODULE_ENABLED
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//#define HAL_HCD_MODULE_ENABLED
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/* ########################## HSE/HSI Values adaptation ##################### */
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/**
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* @brief Adjust the value of External High Speed oscillator (HSE) used in your
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* application. This value is used by the RCC HAL module to compute the system
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* frequency (when HSE is used as system clock source, directly or through the
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* PLL).
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*/
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#if !defined(HSE_VALUE)
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#define HSE_VALUE \
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((uint32_t) 25000000) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined(HSE_STARTUP_TIMEOUT)
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#define HSE_STARTUP_TIMEOUT \
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((uint32_t) 5000) /*!< Time out for HSE start up, in ms */
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#endif /* HSE_STARTUP_TIMEOUT */
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/**
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* @brief Internal High Speed oscillator (HSI) value.
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* This value is used by the RCC HAL module to compute the system
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* frequency (when HSI is used as system clock source, directly or through the
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* PLL).
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*/
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#if !defined(HSI_VALUE)
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#define HSI_VALUE \
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((uint32_t) 16000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @brief Internal Low Speed oscillator (LSI) value.
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*/
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#if !defined(LSI_VALUE)
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#define LSI_VALUE ((uint32_t) 40000)
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#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz \
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The real value may vary depending on the variations \
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in voltage and temperature. */
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/**
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* @brief External Low Speed oscillator (LSE) value.
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*/
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#if !defined(LSE_VALUE)
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#define LSE_VALUE \
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((uint32_t) 32768) /*!< Value of the External Low Speed oscillator in Hz */
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#endif /* LSE_VALUE */
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/**
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* @brief External clock source for I2S peripheral
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* This value is used by the I2S HAL module to compute the I2S clock
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* source frequency, this source is inserted directly through I2S_CKIN pad.
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*/
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#if !defined(EXTERNAL_CLOCK_VALUE)
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#define EXTERNAL_CLOCK_VALUE \
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((uint32_t) 12288000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* EXTERNAL_CLOCK_VALUE */
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/* Tip: To avoid modifying this file each time you need to use different HSE,
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=== you can define the HSE value in your toolchain compiler preprocessor. */
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/* ########################### System Configuration ######################### */
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/**
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* @brief This is the HAL system configuration section
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*/
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#define VDD_VALUE ((uint32_t) 3300) /*!< Value of VDD in mv */
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#define TICK_INT_PRIORITY ((uint32_t) 0x0F) /*!< tick interrupt priority */
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#define USE_RTOS 0
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#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */
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/* ########################## Assert Selection ############################## */
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/**
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* @brief Uncomment the line below to expanse the "assert_param" macro in the
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* HAL drivers code
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*/
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/* #define USE_FULL_ASSERT 1 */
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/* ################## Ethernet peripheral configuration ##################### */
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/* Section 1 : Ethernet peripheral configuration */
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/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
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#define MAC_ADDR0 2
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#define MAC_ADDR1 0
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#define MAC_ADDR2 0
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#define MAC_ADDR3 0
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#define MAC_ADDR4 0
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#define MAC_ADDR5 0
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/* Definition of the Ethernet driver buffers size and count */
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#define ETH_RX_BUF_SIZE \
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ETH_MAX_PACKET_SIZE /* buffer size for receive */
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#define ETH_TX_BUF_SIZE \
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ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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#define ETH_RXBUFNB ((uint32_t) 8) /* 8 Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB ((uint32_t) 4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
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/* Section 2: PHY configuration section */
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/* DP83848 PHY Address*/
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#define DP83848_PHY_ADDRESS 0x01
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/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
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#define PHY_RESET_DELAY ((uint32_t) 0x000000FF)
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/* PHY Configuration delay */
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#define PHY_CONFIG_DELAY ((uint32_t) 0x00000FFF)
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#define PHY_READ_TO ((uint32_t) 0x0000FFFF)
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#define PHY_WRITE_TO ((uint32_t) 0x0000FFFF)
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/* Section 3: Common PHY Registers */
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#define PHY_BCR ((uint16_t) 0x00) /*!< Transceiver Basic Control Register */
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#define PHY_BSR ((uint16_t) 0x01) /*!< Transceiver Basic Status Register */
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#define PHY_RESET ((uint16_t) 0x8000) /*!< PHY Reset */
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#define PHY_LOOPBACK ((uint16_t) 0x4000) /*!< Select loop-back mode */
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#define PHY_FULLDUPLEX_100M \
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((uint16_t) 0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M \
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((uint16_t) 0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M \
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((uint16_t) 0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
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#define PHY_HALFDUPLEX_10M \
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((uint16_t) 0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
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#define PHY_AUTONEGOTIATION \
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((uint16_t) 0x1000) /*!< Enable auto-negotiation function */
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#define PHY_RESTART_AUTONEGOTIATION \
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((uint16_t) 0x0200) /*!< Restart auto-negotiation function */
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#define PHY_POWERDOWN \
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((uint16_t) 0x0800) /*!< Select the power down mode */
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#define PHY_ISOLATE \
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((uint16_t) 0x0400) /*!< Isolate PHY from MII */
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#define PHY_AUTONEGO_COMPLETE \
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((uint16_t) 0x0020) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS \
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((uint16_t) 0x0004) /*!< Valid link established */
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#define PHY_JABBER_DETECTION \
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((uint16_t) 0x0002) /*!< Jabber condition detected */
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/* Section 4: Extended PHY Registers */
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#define PHY_SR \
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((uint16_t) 0x10) /*!< PHY status register Offset */
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#define PHY_MICR \
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((uint16_t) 0x11) /*!< MII Interrupt Control Register */
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#define PHY_MISR \
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((uint16_t) 0x12) /*!< MII Interrupt Status and Misc. Control Register */
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#define PHY_LINK_STATUS \
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((uint16_t) 0x0001) /*!< PHY Link mask */
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#define PHY_SPEED_STATUS \
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((uint16_t) 0x0002) /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS \
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((uint16_t) 0x0004) /*!< PHY Duplex mask */
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#define PHY_MICR_INT_EN \
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((uint16_t) 0x0002) /*!< PHY Enable interrupts */
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#define PHY_MICR_INT_OE \
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((uint16_t) 0x0001) /*!< PHY Enable output interrupt events */
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#define PHY_MISR_LINK_INT_EN \
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((uint16_t) 0x0020) /*!< Enable Interrupt on change of link status */
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#define PHY_LINK_INTERRUPT \
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((uint16_t) 0x2000) /*!< PHY link status interrupt mask */
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#if 0
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#define HAL_ETH_MODULE_ENABLED
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#define HAL_RCC_MODULE_ENABLED
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#define HAL_CORTEX_MODULE_ENABLED
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#define HAL_GPIO_MODULE_ENABLED
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#include "stm32f7xx.h"
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#include "stm32f7xx_hal_cortex.h"
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#include "stm32f7xx_hal_def.h"
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#include "stm32f7xx_hal_rcc.h"
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#define UID_BASE 0x1FF0F420UL
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#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
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#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
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#define ETH_RXBUFNB 3
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#define ETH_TXBUFNB 2
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#define ETH_RX_BUF_SIZE (ipconfigNETWORK_MTU + 36)
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#define ETH_TX_BUF_SIZE (ipconfigNETWORK_MTU + 36)
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#define assert_param(expr) ((void) 0U)
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#define LAN8742A_PHY_ADDRESS 0x00
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#define PHY_RESET_DELAY ((uint32_t)0x00000FFF)
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#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
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#define PHY_READ_TO ((uint32_t)0x0000FFFF)
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#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
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#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
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#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
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#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
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#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
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#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
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#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
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#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
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#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
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#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
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#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
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#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
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#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
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#define PHY_SR ((uint16_t)0x1F) /*!< PHY special control/ status register Offset */
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#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< PHY Duplex mask */
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#define PHY_ISFR ((uint16_t)0x1D) /*!< PHY Interrupt Source Flag register Offset */
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#define PHY_ISFR_INT4 ((uint16_t)0x0010) /*!< PHY Link down inturrupt */
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#if !defined(HSE_VALUE)
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#define HSE_VALUE \
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((uint32_t) 8000000U) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined(HSE_STARTUP_TIMEOUT)
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#define HSE_STARTUP_TIMEOUT \
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((uint32_t) 100U) /*!< Time out for HSE start up, in ms */
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#endif /* HSE_STARTUP_TIMEOUT */
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#if !defined(HSI_VALUE)
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#define HSI_VALUE \
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((uint32_t) 16000000U) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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#if !defined(LSI_VALUE)
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#define LSI_VALUE ((uint32_t) 32000U) /*!< LSI Typical Value in Hz*/
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#endif
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#if !defined(LSE_VALUE)
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#define LSE_VALUE \
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((uint32_t) 32768U) /*!< Value of the External Low Speed oscillator in Hz */
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#endif /* LSE_VALUE */
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#if !defined(LSE_STARTUP_TIMEOUT)
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#define LSE_STARTUP_TIMEOUT \
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((uint32_t) 5000U) /*!< Time out for LSE start up, in ms */
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#endif /* LSE_STARTUP_TIMEOUT */
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#if !defined(EXTERNAL_CLOCK_VALUE)
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#define EXTERNAL_CLOCK_VALUE \
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((uint32_t) 12288000U) /*!< Value of the Internal oscillator in Hz*/
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#endif /* EXTERNAL_CLOCK_VALUE */
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#define VDD_VALUE ((uint32_t) 3300U) /*!< Value of VDD in mv */
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#define TICK_INT_PRIORITY ((uint32_t) 0x0FU) /*!< tick interrupt priority */
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#define USE_RTOS 0U
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#define PREFETCH_ENABLE 1U
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#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch \
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*/
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#endif
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