mongoose/examples/MSP432/ccs/MSP432_MG_hello/MSP_EXP432P401R.cmd
Alexander Alashkin eaef5bd133 Revert "Stop publish examples to mongoose repo"
This reverts commit 1a17e17c462bdd4e1d26d8742f8b7087273e04c2.

PUBLISHED_FROM=80028de308c9a021955d1425d2bfee8feb85f193
2017-02-06 14:08:59 +00:00

62 lines
2.3 KiB
Batchfile

/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== MSP_EXP432P401R.cmd ========
* Define the memory block start/length for the MSP_EXP432P401R M4
*/
MEMORY
{
MAIN (RX) : origin = 0x00000000, length = 0x00040000
INFO (RX) : origin = 0x00200000, length = 0x00004000
SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
}
/* Section allocation in memory */
SECTIONS
{
.text : > MAIN
.const : > MAIN
.cinit : > MAIN
.pinit : > MAIN
.data : > SRAM_DATA
.bss : > SRAM_DATA
.sysmem : > SRAM_DATA
.stack : > SRAM_DATA (HIGH)
}
/* Symbolic definition of the WDTCTL register for RTS */
WDTCTL_SYM = 0x4000480C;