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80 lines
3.9 KiB
C
80 lines
3.9 KiB
C
// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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//
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// This file contains essentials required by the CMSIS:
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// uint32_t SystemCoreClock - holds the system core clock value
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// SystemInit() - initialises the system, e.g. sets up clocks
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#include "hal.h"
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uint32_t SystemCoreClock = SYS_FREQUENCY;
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// - 14.4, Figure 14-2: clock tree
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// - 14.7.4: ARM_PODF defaults to /2; 9.5.3 Table 9-7: ROM agrees
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// - 14.7.5: AHB_PODF defaults to /1; IPG_PODF defaults to /4; PERIPH_CLK_SEL
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// defaults to derive clock from pre_periph_clk_sel
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// - 9.5.3 Table 9-7: ROM changes IPG_PODF to /3
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// - 14.7.6: PRE_PERIPH_CLK_SEL defaults to derive clock from divided
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// PLL1; 9.5.3 Table 9-7: ROM agrees
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// - (For 528MHz operation, we need to set it to derive clock from PLL2)
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// - 14.7.7: PER_CLK defaults to IPG/1; 9.5.3 Table 9-7: ROM changes it to IPG/2
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// - 14.6.1.3.1 ARM PLL (PLL1); 13.3.2.2 PLLs
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// - 14.8.1: PLL1 is powered off and bypassed to 24MHz. Fout = 24MHz *
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// div_select/2
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// - 9.5.3 Table 9-7: ROM enables this PLL and sets it up
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// - For 600MHz operation, we need to set PLL1 on
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// - Datasheet 4.1.3: System frequency/Bus frequency max 600/150MHz respectively
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// (AHB/IPG)
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// - MCUXpresso: IPG_CLK_ROOT <= 150MHz; PERCLK_CLK_ROOT <= 75MHz
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// - Datasheet 4.9.4.1.1/2: the processor clock frequency must exceed twice the
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// ENET_RX_CLK/ENET_TX_CLK frequency.
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// - Datasheet 4.9.4.2: no details for RMII (above is for MII), assumed 50MHz
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// min processor clock
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// - Datasheet 4.1.3, Table 10: "Overdrive" run mode requires 1.25V core voltage
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// minimum; 528 MHz does not.
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void SystemInit(void) { // Called automatically by startup code (ints masked)
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
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asm("DSB");
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asm("ISB");
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// 53.4.2: Disable watchdog after reset (unlocked)
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RTWDOG->CS &= ~RTWDOG_CS_EN_MASK;
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RTWDOG->TOVAL = 0xFFFF;
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while (RTWDOG->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock
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while ((RTWDOG->CS & RTWDOG_CS_RCS_MASK) == 0)
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spin(1); // wait for new config
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// Set VDD_SOC to 1.25V
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SETBITS(DCDC->REG3, DCDC_REG3_TRG_MASK, DCDC_REG3_TRG(0x12));
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while ((DCDC->REG0 & DCDC_REG0_STS_DC_OK_MASK) == 0)
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spin(1); // Wait for DCDC_STS_DC_OK
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// ROM fiddles with AHB divider, wait and then keep bits at 0 (expected)
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while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_MASK) spin(1);
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SETBITS(CCM->CBCDR, CCM_CBCDR_IPG_PODF_MASK | CCM_CBCDR_AHB_PODF_MASK,
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CCM_CBCDR_IPG_PODF(3)); // keep AHB, set IPG divider /4 (150MHz)
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SETBITS(CCM->CSCMR1, CCM_CSCMR1_PERCLK_PODF_MASK,
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CCM_CSCMR1_PERCLK_PODF(1)); // Set PERCLK divider /2 (75MHz)
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// Set clock to 600 MHz. Power PLL on and configure divider (ROM boot code
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// fiddles with the PLL, bypass first)
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CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_BYPASS_MASK;
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SETBITS(CCM_ANALOG->PLL_ARM,
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CCM_ANALOG_PLL_ARM_POWERDOWN_MASK |
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CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK,
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CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(100));
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while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0)
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spin(1); // wait until it is stable
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CCM_ANALOG->PLL_ARM &=
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~CCM_ANALOG_PLL_ARM_BYPASS_MASK; // Disable Bypass (switch to PLL)
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// 14.5 Table 14-4: uart_clk_root
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// 14.4: uart_clk_root = PLL3/6 or OSC; CCM_CSCDR1 (14.7.9) defaults to
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// PLL3/6/1; but ROM boot code fiddles with the divider (9.5.3 Table 9-7)
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CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_POWER_MASK; // Power PLL on
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while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0)
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spin(1); // wait until it is stable
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CCM_ANALOG->PLL_USB1 &=
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~CCM_ANALOG_PLL_USB1_BYPASS_MASK; // Disable Bypass (switch to PLL)
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CCM->CSCDR1 &=
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~(CCM_CSCDR1_UART_CLK_SEL_MASK | CCM_CSCDR1_UART_CLK_PODF_MASK);
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rng_init(); // Initialise random number generator
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// NXP startup code calls SystemInit BEFORE initializing RAM...
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SysTick_Config(SYS_FREQUENCY / 1000); // Sys tick every 1ms
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}
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