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35 lines
1.2 KiB
Plaintext
35 lines
1.2 KiB
Plaintext
ENTRY(Reset_Handler);
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MEMORY {
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flash(rx) : ORIGIN = 0x08000000, LENGTH = 1024k
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sram(rwx) : ORIGIN = 0x24000000, LENGTH = 128k /* AXI SRAM in domain D1 */
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/* 2.3.2: remaining SRAM is in other (non-contiguous) banks,
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DTCM @0x20000000 is in domain D1 and not accessible by the ETH DMA controller in domain D2
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@0x24020000 can be either AXI or ITCM (2.4 Table 8)
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SRAM @0x30000000 is in domain D2 and not directly available at startup to be used as stack (8.5.9 page 366)
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SRAM @0x38000000 is in domain D3 and not directly available at startup to be used as stack (8.5.9 page 366) */
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}
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_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
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SECTIONS {
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.vectors : { KEEP(*(.isr_vector)) } > flash
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.text : { *(.text* .text.*) } > flash
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.rodata : { *(.rodata*) } > flash
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.data : {
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_sdata = .; /* for init_ram() */
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*(.first_data)
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*(.data SORT(.data.*))
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_edata = .; /* for init_ram() */
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} > sram AT > flash
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_sidata = LOADADDR(.data);
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.bss : {
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_sbss = .; /* for init_ram() */
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*(.bss SORT(.bss.*) COMMON)
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_ebss = .; /* for init_ram() */
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} > sram
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. = ALIGN(8);
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_end = .; /* for cmsis_gcc.h and init_ram() */
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}
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