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c2068d08f0
*) Change: the "bl" and "af" parameters of the "listen" directive was
renamed to the "backlog" and "accept_filter".
*) Feature: the "rcvbuf" and "sndbuf" parameters of the "listen"
directive.
*) Change: the "$msec" log parameter does not require now the
additional the gettimeofday() system call.
*) Feature: the -t switch now tests the "listen" directives.
*) Bugfix: if the invalid address was specified in the "listen"
directive, then after the -HUP signal nginx left an open socket in
the CLOSED state.
*) Bugfix: the mime type may be incorrectly set to default value for
index file with variable in the name; the bug had appeared in 0.3.0.
*) Feature: the "timer_resolution" directive.
*) Feature: the millisecond "$upstream_response_time" log parameter.
*) Bugfix: a temporary file with client request body now is removed
just after the response header was transferred to a client.
*) Bugfix: OpenSSL 0.9.6 compatibility.
*) Bugfix: the SSL certificate and key file paths could not be relative.
*) Bugfix: the "ssl_prefer_server_ciphers" directive did not work in
the ngx_imap_ssl_module.
*) Bugfix: the "ssl_protocols" directive allowed to specify the single
protocol only.
112 lines
2.1 KiB
C
112 lines
2.1 KiB
C
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/*
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* Copyright (C) Igor Sysoev
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*/
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#if (NGX_SMP)
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#define NGX_SMP_LOCK "lock;"
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#else
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#define NGX_SMP_LOCK
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#endif
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/*
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* "cmpxchgl r, [m]":
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*
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* if (eax == [m]) {
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* zf = 1;
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* [m] = r;
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* } else {
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* zf = 0;
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* eax = [m];
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* }
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*
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*
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* The "q" is any of the %eax, %ebx, %ecx, or %edx registers.
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* The "=a" and "a" are the %eax register. Although we can return result
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* in any register, we use %eax because it is used in cmpxchgl anyway.
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* The "cc" means that flags were changed.
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*/
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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{
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ngx_atomic_uint_t res;
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__asm__ volatile (
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NGX_SMP_LOCK
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" cmpxchgl %3, %1; "
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" setz %b0; "
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" movzbl %b0, %0; "
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: "=a" (res) : "m" (*lock), "a" (old), "q" (set) : "cc", "memory");
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return res;
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}
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/*
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* "xaddl r, [m]":
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*
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* temp = [m];
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* [m] += r;
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* r = temp;
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*
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*
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* The "+q" is any of the %eax, %ebx, %ecx, or %edx registers.
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* The "cc" means that flags were changed.
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*/
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#if !(__GNUC__ == 2 && __GNUC_MINOR__ <= 7)
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static ngx_inline ngx_atomic_int_t
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ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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{
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__asm__ volatile (
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NGX_SMP_LOCK
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" xaddl %0, %1; "
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: "+q" (add) : "m" (*value) : "cc", "memory");
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return add;
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}
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#else /* (__GNUC__ == 2 && __GNUC_MINOR__ <= 7) */
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/*
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* gcc 2.7 does not support "+q", so we have to use the fixed %eax ("=a" and
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* "a") and this adds two superfluous instructions in the end of code,
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* something like this: "mov %eax, %edx / mov %edx, %eax".
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*/
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static ngx_inline ngx_atomic_int_t
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ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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{
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ngx_atomic_uint_t old;
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__asm__ volatile (
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NGX_SMP_LOCK
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" xaddl %2, %1; "
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: "=a" (old) : "m" (*value), "a" (add) : "cc", "memory");
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return old;
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}
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#endif
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/*
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* on x86 the write operations go in a program order, so we need only
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* to disable the gcc reorder optimizations
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*/
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#define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
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