mirror of
https://github.com/nginx/nginx.git
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140 lines
2.4 KiB
C
140 lines
2.4 KiB
C
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/*
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* Copyright (C) Igor Sysoev
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* Copyright (C) Nginx, Inc.
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*/
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#include <ngx_config.h>
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#include <ngx_core.h>
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#if (( __i386__ || __amd64__ ) && ( __GNUC__ || __INTEL_COMPILER ))
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static ngx_inline void ngx_cpuid(uint32_t i, uint32_t *buf);
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#if ( __i386__ )
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static ngx_inline void
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ngx_cpuid(uint32_t i, uint32_t *buf)
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{
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/*
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* we could not use %ebx as output parameter if gcc builds PIC,
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* and we could not save %ebx on stack, because %esp is used,
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* when the -fomit-frame-pointer optimization is specified.
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*/
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__asm__ (
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" mov %%ebx, %%esi; "
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" cpuid; "
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" mov %%eax, (%1); "
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" mov %%ebx, 4(%1); "
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" mov %%edx, 8(%1); "
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" mov %%ecx, 12(%1); "
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" mov %%esi, %%ebx; "
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: : "a" (i), "D" (buf) : "ecx", "edx", "esi", "memory" );
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}
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#else /* __amd64__ */
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static ngx_inline void
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ngx_cpuid(uint32_t i, uint32_t *buf)
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{
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uint32_t eax, ebx, ecx, edx;
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__asm__ (
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"cpuid"
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (i) );
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buf[0] = eax;
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buf[1] = ebx;
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buf[2] = edx;
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buf[3] = ecx;
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}
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#endif
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/* auto detect the L2 cache line size of modern and widespread CPUs */
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void
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ngx_cpuinfo(void)
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{
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u_char *vendor;
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uint32_t vbuf[5], cpu[4], model;
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vbuf[0] = 0;
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vbuf[1] = 0;
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vbuf[2] = 0;
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vbuf[3] = 0;
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vbuf[4] = 0;
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ngx_cpuid(0, vbuf);
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vendor = (u_char *) &vbuf[1];
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if (vbuf[0] == 0) {
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return;
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}
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ngx_cpuid(1, cpu);
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if (ngx_strcmp(vendor, "GenuineIntel") == 0) {
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switch ((cpu[0] & 0xf00) >> 8) {
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/* Pentium */
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case 5:
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ngx_cacheline_size = 32;
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break;
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/* Pentium Pro, II, III */
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case 6:
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ngx_cacheline_size = 32;
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model = ((cpu[0] & 0xf0000) >> 8) | (cpu[0] & 0xf0);
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if (model >= 0xd0) {
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/* Intel Core, Core 2, Atom */
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ngx_cacheline_size = 64;
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}
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break;
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/*
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* Pentium 4, although its cache line size is 64 bytes,
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* it prefetches up to two cache lines during memory read
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*/
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case 15:
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ngx_cacheline_size = 128;
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break;
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}
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} else if (ngx_strcmp(vendor, "AuthenticAMD") == 0) {
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ngx_cacheline_size = 64;
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}
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}
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#else
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void
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ngx_cpuinfo(void)
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{
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}
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#endif
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