mirror of
https://github.com/nginx/nginx.git
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ffe714403d
*) Change: the "variables_hash_max_size" and
"variables_hash_bucket_size" directives.
*) Feature: the $body_bytes_sent variable can be used not only in the
"log_format" directive.
*) Feature: the $ssl_protocol and $ssl_cipher variables.
*) Feature: the cache line size detection for widespread CPUs at start
time.
*) Feature: now the "accept_mutex" directive is supported using
fcntl(2) on platforms different from i386, amd64, sparc64, and ppc.
*) Feature: the "lock_file" directive and the --with-lock-path=PATH
autoconfiguration directive.
*) Bugfix: if the HTTPS protocol was used in the "proxy_pass" directive
then the requests with the body was not transferred.
124 lines
2.5 KiB
C
124 lines
2.5 KiB
C
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/*
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* Copyright (C) Igor Sysoev
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*/
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#if (NGX_SMP)
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#define NGX_SMP_LOCK "lock;"
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#else
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#define NGX_SMP_LOCK
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#endif
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/*
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* "cmpxchgl r, [m]":
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*
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* if (eax == [m]) {
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* zf = 1;
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* [m] = r;
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* } else {
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* zf = 0;
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* eax = [m];
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* }
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*
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*
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* The "q" is any of the %eax, %ebx, %ecx, or %edx registers.
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* The "=a" and "a" are the %eax register. Although we can return result
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* in any register, we use %eax because it is used in cmpxchgl anyway.
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* The "cc" means that flags were changed.
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*/
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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{
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ngx_atomic_uint_t res;
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__asm__ volatile (
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NGX_SMP_LOCK
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" cmpxchgl %3, %1; "
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" setz %b0; "
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" movzbl %b0, %0; "
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: "=a" (res) : "m" (*lock), "a" (old), "q" (set) : "cc", "memory");
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return res;
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}
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/*
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* "xaddl r, [m]":
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*
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* temp = [m];
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* [m] += r;
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* r = temp;
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*
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*
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* The "+q" is any of the %eax, %ebx, %ecx, or %edx registers.
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* The "cc" means that flags were changed.
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*/
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#if !(( __GNUC__ == 2 && __GNUC_MINOR__ <= 7 ) || ( __INTEL_COMPILER >= 800 ))
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/*
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* icc 8.1 and 9.0 compile broken code with -march=pentium4 option:
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* ngx_atomic_fetch_add() always return the input "add" value,
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* so we use the gcc 2.7 version.
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*
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* icc 8.1 and 9.0 with -march=pentiumpro option or icc 7.1 compile
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* correct code.
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*/
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static ngx_inline ngx_atomic_int_t
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ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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{
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__asm__ volatile (
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NGX_SMP_LOCK
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" xaddl %0, %1; "
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: "+q" (add) : "m" (*value) : "cc", "memory");
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return add;
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}
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#else
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/*
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* gcc 2.7 does not support "+q", so we have to use the fixed %eax ("=a" and
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* "a") and this adds two superfluous instructions in the end of code,
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* something like this: "mov %eax, %edx / mov %edx, %eax".
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*/
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static ngx_inline ngx_atomic_int_t
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ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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{
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ngx_atomic_uint_t old;
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__asm__ volatile (
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NGX_SMP_LOCK
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" xaddl %2, %1; "
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: "=a" (old) : "m" (*value), "a" (add) : "cc", "memory");
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return old;
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}
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#endif
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/*
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* on x86 the write operations go in a program order, so we need only
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* to disable the gcc reorder optimizations
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*/
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#define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
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/* old as does not support "pause" opcode */
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#define ngx_cpu_pause() __asm__ (".byte 0xf3, 0x90")
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