mirror of
https://github.com/nginx/nginx.git
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11d753231b
*) Feature: the ngx_http_ssi_filter_module and the ssi,
ssi_silent_errors, and ssi_min_file_chunk directives. The 'echo
var="HTTP_..." default=""' and 'echo var="REMOTE_ADDR"' commands are
supported.
*) Feature: the %request_time log parameter.
*) Feature: if the request has no the "Host" header line, then the
"proxy_preserve_host" directive set this header line to the first
server name of the "server_name" directive.
*) Bugfix: nginx could not be built on platforms different from i386,
amd64, sparc, and ppc; the bug had appeared in 0.1.22.
*) Bugfix: the ngx_http_autoindex_module now shows the information not
about the symlink, but about file or directory it points to.
*) Bugfix: the %apache_length parameter logged the negative length of
the response header if the no response was transferred to a client.
414 lines
9.1 KiB
C
414 lines
9.1 KiB
C
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/*
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* Copyright (C) Igor Sysoev
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*/
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#ifndef _NGX_ATOMIC_H_INCLUDED_
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#define _NGX_ATOMIC_H_INCLUDED_
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#include <ngx_config.h>
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#include <ngx_core.h>
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#if ( __i386__ )
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#define NGX_HAVE_ATOMIC_OPS 1
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typedef int32_t ngx_atomic_int_t;
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typedef uint32_t ngx_atomic_uint_t;
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typedef volatile ngx_atomic_uint_t ngx_atomic_t;
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#define NGX_ATOMIC_T_LEN sizeof("-2147483648") - 1
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#if (NGX_SMP)
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#define NGX_SMP_LOCK "lock;"
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#else
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#define NGX_SMP_LOCK
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#endif
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/*
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* the "=q" is any of the %eax, %ebx, %ecx, or %edx registers.
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* the '"0" (1)' parameter preloads 1 into %0.
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* the "cc" means that flags were changed.
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*
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* "xadd r, [m]":
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*
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* temp = [m];
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* [m] += r;
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* r = temp;
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*/
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_inc(ngx_atomic_t *value)
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{
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ngx_atomic_uint_t old;
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__asm__ volatile (
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NGX_SMP_LOCK
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" xaddl %0, %2; "
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" incl %0; "
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: "=q" (old) : "0" (1), "m" (*value) : "cc", "memory");
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return old;
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}
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_dec(ngx_atomic_t *value)
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{
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ngx_atomic_uint_t old;
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__asm__ volatile (
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NGX_SMP_LOCK
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" xaddl %0, %2; "
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" decl %0; "
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: "=q" (old) : "0" (-1), "m" (*value) : "cc", "memory");
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return old;
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}
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/*
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* the "q" is any of the %eax, %ebx, %ecx, or %edx registers.
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* the "=a" and "a" are the %eax register. Although we can return result
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* in any register, we use %eax because it is used in cmpxchg anyway.
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*
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* "cmpxchg r, [m]":
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*
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* if (eax == [m]) {
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* zf = 1;
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* [m] = r;
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* } else {
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* zf = 0;
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* eax = [m];
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* }
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*/
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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{
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ngx_atomic_uint_t res;
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__asm__ volatile (
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NGX_SMP_LOCK
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" cmpxchgl %3, %1; "
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" setz %b0; "
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" movzbl %b0, %0; "
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: "=a" (res) : "m" (*lock), "a" (old), "q" (set) : "cc", "memory");
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return res;
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}
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#elif ( __amd64__ )
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#define NGX_HAVE_ATOMIC_OPS 1
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typedef int64_t ngx_atomic_int_t;
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typedef uint64_t ngx_atomic_uint_t;
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typedef volatile ngx_atomic_uint_t ngx_atomic_t;
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#define NGX_ATOMIC_T_LEN sizeof("-9223372036854775808") - 1
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#if (NGX_SMP)
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#define NGX_SMP_LOCK "lock;"
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#else
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#define NGX_SMP_LOCK
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#endif
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_inc(ngx_atomic_t *value)
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{
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ngx_atomic_uint_t old;
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__asm__ volatile (
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NGX_SMP_LOCK
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" xaddq %0, %2; "
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" incq %0; "
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: "=r" (old) : "0" (1), "m" (*value) : "cc", "memory");
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return old;
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}
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/* the '"0" (-1LL)' parameter preloads -1 into the 64-bit %0 register */
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_dec(ngx_atomic_t *value)
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{
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ngx_atomic_uint_t old;
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__asm__ volatile (
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NGX_SMP_LOCK
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" xaddq %0, %2; "
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" decq %0; "
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: "=r" (old) : "0" (-1LL), "m" (*value) : "cc", "memory");
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return old;
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}
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/* the "=a" and "a" are the %rax register. */
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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{
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ngx_atomic_uint_t res;
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__asm__ volatile (
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NGX_SMP_LOCK
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" cmpxchgq %3, %1; "
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" setz %b0; "
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" movzbq %b0, %0; "
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: "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");
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return res;
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}
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#elif ( __sparc__ )
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#define NGX_HAVE_ATOMIC_OPS 1
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#if (NGX_PTR_SIZE == 8)
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typedef int64_t ngx_atomic_int_t;
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typedef uint64_t ngx_atomic_uint_t;
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#define NGX_ATOMIC_T_LEN sizeof("-9223372036854775808") - 1
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#define NGX_CASXA "casxa"
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#else
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typedef int32_t ngx_atomic_int_t;
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typedef uint32_t ngx_atomic_uint_t;
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#define NGX_ATOMIC_T_LEN sizeof("-2147483648") - 1
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#define NGX_CASXA "casa"
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#endif
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typedef volatile ngx_atomic_uint_t ngx_atomic_t;
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/*
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* the "+r" means the general register used for both input and output.
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*
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* "casa [r1] 0x80, r2, r0" and
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* "casxa [r1] 0x80, r2, r0" do the following:
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*
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* if ([r1] == r2) {
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* swap(r0, [r1]);
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* } else {
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* r0 = [r1];
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* }
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*
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* so "r0 == r2" means that the operation was successfull.
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*/
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_inc(ngx_atomic_t *value)
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{
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ngx_atomic_uint_t old, new, res;
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old = *value;
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for ( ;; ) {
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new = old + 1;
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res = new;
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__asm__ volatile (
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NGX_CASXA " [%1] 0x80, %2, %0"
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: "+r" (res) : "r" (value), "r" (old) : "memory");
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if (res == old) {
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return new;
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}
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old = res;
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}
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}
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_dec(ngx_atomic_t *value)
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{
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ngx_atomic_uint_t old, new, res;
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old = *value;
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for ( ;; ) {
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new = old - 1;
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res = new;
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__asm__ volatile (
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NGX_CASXA " [%1] 0x80, %2, %0"
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: "+r" (res) : "r" (value), "r" (old) : "memory");
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if (res == old) {
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return new;
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}
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old = res;
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}
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}
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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{
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__asm__ volatile (
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NGX_CASXA " [%1] 0x80, %2, %0"
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: "+r" (set) : "r" (lock), "r" (old) : "memory");
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return (set == old);
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}
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#elif ( __ppc__ )
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#define NGX_HAVE_ATOMIC_OPS 1
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#if (NGX_PTR_SIZE == 8)
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typedef int64_t ngx_atomic_int_t;
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typedef uint64_t ngx_atomic_uint_t;
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#define NGX_ATOMIC_T_LEN sizeof("-9223372036854775808") - 1
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#else
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typedef int32_t ngx_atomic_int_t;
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typedef uint32_t ngx_atomic_uint_t;
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#define NGX_ATOMIC_T_LEN sizeof("-2147483648") - 1
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#endif
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typedef volatile ngx_atomic_uint_t ngx_atomic_t;
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/*
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* the ppc assembler treats ";" as comment, so we have to use "\n".
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* the minus in "bne-" is a hint for the branch prediction unit that
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* this branch is unlikely to be taken.
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*
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* the "=&r" means that no input registers can be used.
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* the "=&b" means that the base registers can be used only, i.e. any register
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* except r0. the r0 register can not be used in "addi r0, r0, 1".
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* the "1b" means the nearest backward label "1" and the "1f" means
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* the nearest forward label "1".
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*/
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_inc(ngx_atomic_t *value)
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{
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ngx_atomic_uint_t res;
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__asm__ volatile (
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"1: lwarx %0, 0, %1 \n" /* load from [value] into "res" */
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/* and store reservation */
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" addi %0, %0, 1 \n" /* add "1" to "res" */
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" stwcx. %0, 0, %1 \n" /* store "res" into [value] if reservation */
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/* is not cleared */
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" bne- 1b \n" /* try again if reservation was cleared */
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: "=&b" (res) : "r" (value) : "cc", "memory");
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return res;
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}
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_dec(ngx_atomic_t *value)
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{
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ngx_atomic_uint_t res;
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__asm__ volatile (
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"1: lwarx %0, 0, %1 \n" /* load from [value] into "res" */
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/* and store reservation */
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" addi %0, %0, -1 \n" /* sub "1" from "res" */
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" stwcx. %0, 0, %1 \n" /* store "res" into [value] if reservation */
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/* is not cleared */
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" bne- 1b \n" /* try again if reservation was cleared */
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: "=&b" (res) : "r" (value) : "cc", "memory");
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return res;
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}
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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{
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ngx_atomic_uint_t res, temp;
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__asm__ volatile (
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" li %0, 0 \n" /* preset "0" to "res" */
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" lwarx %1, 0, %2 \n" /* load from [lock] into "temp" */
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/* and store reservation */
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" cmpw %1, %3 \n" /* compare "temp" and "old" */
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" bne- 1f \n" /* not equal */
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" stwcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */
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/* is not cleared */
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" bne- 1f \n" /* the reservation was cleared */
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" li %0, 1 \n" /* set "1" to "res" */
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"1: \n"
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: "=&r" (res), "=&r" (temp)
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: "r" (lock), "r" (old), "r" (set)
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: "cc", "memory");
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return res;
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}
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#else
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#define NGX_HAVE_ATOMIC_OPS 0
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typedef int32_t ngx_atomic_int_t;
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typedef uint32_t ngx_atomic_uint_t;
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typedef volatile ngx_atomic_uint_t ngx_atomic_t;
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#define NGX_ATOMIC_T_LEN sizeof("-2147483648") - 1
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#define ngx_atomic_inc(x) ++(*(x))
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#define ngx_atomic_dec(x) --(*(x))
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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{
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*lock = set;
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return 1;
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}
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#endif
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void ngx_spinlock(ngx_atomic_t *lock, ngx_uint_t spin);
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#define ngx_trylock(lock) (*(lock) == 0 && ngx_atomic_cmp_set(lock, 0, 1))
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#define ngx_unlock(lock) *(lock) = 0
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#endif /* _NGX_ATOMIC_H_INCLUDED_ */
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