mirror of
https://github.com/nginx/nginx.git
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155 lines
5.5 KiB
C
155 lines
5.5 KiB
C
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/*
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* Copyright (C) Igor Sysoev
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*/
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/*
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* The ppc assembler treats ";" as comment, so we have to use "\n".
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* The minus in "bne-" is a hint for the branch prediction unit that
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* this branch is unlikely to be taken.
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* The "1b" means the nearest backward label "1" and the "1f" means
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* the nearest forward label "1".
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*
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* The "b" means that the base registers can be used only, i.e.
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* any register except r0. The r0 register always has a zero value and
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* could not be used in "addi r0, r0, 1".
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* The "=&b" means that no input registers can be used.
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*
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* "sync" read and write barriers
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* "isync" read barrier, is faster than "sync"
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* "eieio" write barrier, is faster than "sync"
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* "lwsync" write barrier, is faster than "eieio" on ppc64
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*/
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#if (NGX_PTR_SIZE == 8)
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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{
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ngx_atomic_uint_t res, temp;
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__asm__ volatile (
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" li %0, 0 \n" /* preset "0" to "res" */
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" lwsync \n" /* write barrier */
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"1: \n"
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" ldarx %1, 0, %2 \n" /* load from [lock] into "temp" */
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/* and store reservation */
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" cmpd %1, %3 \n" /* compare "temp" and "old" */
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" bne- 2f \n" /* not equal */
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" stdcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */
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/* is not cleared */
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" bne- 1b \n" /* the reservation was cleared */
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" isync \n" /* read barrier */
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" li %0, 1 \n" /* set "1" to "res" */
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"2: \n"
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: "=&b" (res), "=&b" (temp)
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: "b" (lock), "b" (old), "b" (set)
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: "cc", "memory");
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return res;
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}
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static ngx_inline ngx_atomic_int_t
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ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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{
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ngx_atomic_uint_t res, temp;
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__asm__ volatile (
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" lwsync \n" /* write barrier */
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"1: ldarx %0, 0, %2 \n" /* load from [value] into "res" */
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/* and store reservation */
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" add %1, %0, %3 \n" /* "res" + "add" store in "temp" */
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" stdcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */
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/* is not cleared */
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" bne- 1b \n" /* try again if reservation was cleared */
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" isync \n" /* read barrier */
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: "=&b" (res), "=&b" (temp)
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: "b" (value), "b" (add)
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: "cc", "memory");
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return res;
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}
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#if (NGX_SMP)
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#define ngx_memory_barrier() \
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__asm__ volatile ("isync \n lwsync \n" ::: "memory")
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#else
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#define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
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#endif
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#else
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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{
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ngx_atomic_uint_t res, temp;
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__asm__ volatile (
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" li %0, 0 \n" /* preset "0" to "res" */
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" eieio \n" /* write barrier */
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"1: \n"
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" lwarx %1, 0, %2 \n" /* load from [lock] into "temp" */
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/* and store reservation */
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" cmpw %1, %3 \n" /* compare "temp" and "old" */
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" bne- 2f \n" /* not equal */
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" stwcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */
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/* is not cleared */
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" bne- 1b \n" /* the reservation was cleared */
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" isync \n" /* read barrier */
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" li %0, 1 \n" /* set "1" to "res" */
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"2: \n"
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: "=&b" (res), "=&b" (temp)
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: "b" (lock), "b" (old), "b" (set)
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: "cc", "memory");
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return res;
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}
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static ngx_inline ngx_atomic_int_t
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ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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{
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ngx_atomic_uint_t res, temp;
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__asm__ volatile (
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" eieio \n" /* write barrier */
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"1: lwarx %0, 0, %2 \n" /* load from [value] into "res" */
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/* and store reservation */
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" add %1, %0, %3 \n" /* "res" + "add" store in "temp" */
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" stwcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */
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/* is not cleared */
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" bne- 1b \n" /* try again if reservation was cleared */
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" isync \n" /* read barrier */
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: "=&b" (res), "=&b" (temp)
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: "b" (value), "b" (add)
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: "cc", "memory");
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return res;
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}
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#if (NGX_SMP)
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#define ngx_memory_barrier() \
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__asm__ volatile ("isync \n eieio \n" ::: "memory")
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#else
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#define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
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#endif
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#endif
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#define ngx_cpu_pause()
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