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hog
This commit is contained in:
Vladislav Vinogradov
parent
0ddd16cf78
commit
0e339dd137
@ -42,7 +42,10 @@
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#if !defined CUDA_DISABLER
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#include "internal_shared.hpp"
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#include "opencv2/gpu/device/common.hpp"
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#include "opencv2/gpu/device/reduce.hpp"
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#include "opencv2/gpu/device/functional.hpp"
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#include "opencv2/gpu/device/warp_shuffle.hpp"
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namespace cv { namespace gpu { namespace device
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{
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@ -226,29 +229,30 @@ namespace cv { namespace gpu { namespace device
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template<int size>
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__device__ float reduce_smem(volatile float* smem)
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__device__ float reduce_smem(float* smem, float val)
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{
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unsigned int tid = threadIdx.x;
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float sum = smem[tid];
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float sum = val;
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if (size >= 512) { if (tid < 256) smem[tid] = sum = sum + smem[tid + 256]; __syncthreads(); }
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if (size >= 256) { if (tid < 128) smem[tid] = sum = sum + smem[tid + 128]; __syncthreads(); }
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if (size >= 128) { if (tid < 64) smem[tid] = sum = sum + smem[tid + 64]; __syncthreads(); }
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reduce<size>(smem, sum, tid, plus<float>());
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if (tid < 32)
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if (size == 32)
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{
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if (size >= 64) smem[tid] = sum = sum + smem[tid + 32];
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if (size >= 32) smem[tid] = sum = sum + smem[tid + 16];
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if (size >= 16) smem[tid] = sum = sum + smem[tid + 8];
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if (size >= 8) smem[tid] = sum = sum + smem[tid + 4];
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if (size >= 4) smem[tid] = sum = sum + smem[tid + 2];
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if (size >= 2) smem[tid] = sum = sum + smem[tid + 1];
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#if __CUDA_ARCH__ >= 300
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return shfl(sum, 0);
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#else
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return smem[0];
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#endif
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}
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__syncthreads();
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sum = smem[0];
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#if __CUDA_ARCH__ >= 300
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if (threadIdx.x == 0)
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smem[0] = sum;
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#endif
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return sum;
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__syncthreads();
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return smem[0];
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}
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@ -272,19 +276,13 @@ namespace cv { namespace gpu { namespace device
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if (threadIdx.x < block_hist_size)
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elem = hist[0];
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squares[threadIdx.x] = elem * elem;
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__syncthreads();
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float sum = reduce_smem<nthreads>(squares);
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float sum = reduce_smem<nthreads>(squares, elem * elem);
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float scale = 1.0f / (::sqrtf(sum) + 0.1f * block_hist_size);
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elem = ::min(elem * scale, threshold);
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__syncthreads();
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squares[threadIdx.x] = elem * elem;
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sum = reduce_smem<nthreads>(squares, elem * elem);
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__syncthreads();
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sum = reduce_smem<nthreads>(squares);
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scale = 1.0f / (::sqrtf(sum) + 1e-3f);
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if (threadIdx.x < block_hist_size)
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@ -330,65 +328,36 @@ namespace cv { namespace gpu { namespace device
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// return confidence values not just positive location
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template <int nthreads, // Number of threads per one histogram block
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int nblocks> // Number of histogram block processed by single GPU thread block
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int nblocks> // Number of histogram block processed by single GPU thread block
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__global__ void compute_confidence_hists_kernel_many_blocks(const int img_win_width, const int img_block_width,
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const int win_block_stride_x, const int win_block_stride_y,
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const float* block_hists, const float* coefs,
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float free_coef, float threshold, float* confidences)
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{
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const int win_x = threadIdx.z;
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if (blockIdx.x * blockDim.z + win_x >= img_win_width)
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return;
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const int win_x = threadIdx.z;
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if (blockIdx.x * blockDim.z + win_x >= img_win_width)
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return;
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const float* hist = block_hists + (blockIdx.y * win_block_stride_y * img_block_width +
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blockIdx.x * win_block_stride_x * blockDim.z + win_x) *
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cblock_hist_size;
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const float* hist = block_hists + (blockIdx.y * win_block_stride_y * img_block_width +
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blockIdx.x * win_block_stride_x * blockDim.z + win_x) *
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cblock_hist_size;
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float product = 0.f;
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for (int i = threadIdx.x; i < cdescr_size; i += nthreads)
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{
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int offset_y = i / cdescr_width;
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int offset_x = i - offset_y * cdescr_width;
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product += coefs[i] * hist[offset_y * img_block_width * cblock_hist_size + offset_x];
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}
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float product = 0.f;
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for (int i = threadIdx.x; i < cdescr_size; i += nthreads)
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{
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int offset_y = i / cdescr_width;
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int offset_x = i - offset_y * cdescr_width;
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product += coefs[i] * hist[offset_y * img_block_width * cblock_hist_size + offset_x];
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}
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__shared__ float products[nthreads * nblocks];
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__shared__ float products[nthreads * nblocks];
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const int tid = threadIdx.z * nthreads + threadIdx.x;
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products[tid] = product;
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const int tid = threadIdx.z * nthreads + threadIdx.x;
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__syncthreads();
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reduce<nthreads>(products, product, tid, plus<float>());
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if (nthreads >= 512)
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{
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if (threadIdx.x < 256) products[tid] = product = product + products[tid + 256];
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__syncthreads();
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}
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if (nthreads >= 256)
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{
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if (threadIdx.x < 128) products[tid] = product = product + products[tid + 128];
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__syncthreads();
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}
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if (nthreads >= 128)
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{
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if (threadIdx.x < 64) products[tid] = product = product + products[tid + 64];
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__syncthreads();
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}
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if (threadIdx.x < 32)
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{
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volatile float* smem = products;
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if (nthreads >= 64) smem[tid] = product = product + smem[tid + 32];
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if (nthreads >= 32) smem[tid] = product = product + smem[tid + 16];
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if (nthreads >= 16) smem[tid] = product = product + smem[tid + 8];
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if (nthreads >= 8) smem[tid] = product = product + smem[tid + 4];
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if (nthreads >= 4) smem[tid] = product = product + smem[tid + 2];
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if (nthreads >= 2) smem[tid] = product = product + smem[tid + 1];
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}
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if (threadIdx.x == 0)
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confidences[blockIdx.y * img_win_width + blockIdx.x * blockDim.z + win_x]
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= (float)(product + free_coef);
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if (threadIdx.x == 0)
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confidences[blockIdx.y * img_win_width + blockIdx.x * blockDim.z + win_x] = product + free_coef;
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}
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@ -396,32 +365,32 @@ namespace cv { namespace gpu { namespace device
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int win_stride_y, int win_stride_x, int height, int width, float* block_hists,
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float* coefs, float free_coef, float threshold, float *confidences)
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{
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const int nthreads = 256;
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const int nblocks = 1;
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const int nthreads = 256;
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const int nblocks = 1;
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int win_block_stride_x = win_stride_x / block_stride_x;
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int win_block_stride_y = win_stride_y / block_stride_y;
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int img_win_width = (width - win_width + win_stride_x) / win_stride_x;
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int img_win_height = (height - win_height + win_stride_y) / win_stride_y;
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int win_block_stride_x = win_stride_x / block_stride_x;
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int win_block_stride_y = win_stride_y / block_stride_y;
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int img_win_width = (width - win_width + win_stride_x) / win_stride_x;
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int img_win_height = (height - win_height + win_stride_y) / win_stride_y;
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dim3 threads(nthreads, 1, nblocks);
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dim3 grid(divUp(img_win_width, nblocks), img_win_height);
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dim3 threads(nthreads, 1, nblocks);
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dim3 grid(divUp(img_win_width, nblocks), img_win_height);
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cudaSafeCall(cudaFuncSetCacheConfig(compute_confidence_hists_kernel_many_blocks<nthreads, nblocks>,
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cudaFuncCachePreferL1));
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cudaSafeCall(cudaFuncSetCacheConfig(compute_confidence_hists_kernel_many_blocks<nthreads, nblocks>,
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cudaFuncCachePreferL1));
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int img_block_width = (width - CELLS_PER_BLOCK_X * CELL_WIDTH + block_stride_x) /
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block_stride_x;
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compute_confidence_hists_kernel_many_blocks<nthreads, nblocks><<<grid, threads>>>(
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img_win_width, img_block_width, win_block_stride_x, win_block_stride_y,
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block_hists, coefs, free_coef, threshold, confidences);
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cudaSafeCall(cudaThreadSynchronize());
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int img_block_width = (width - CELLS_PER_BLOCK_X * CELL_WIDTH + block_stride_x) /
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block_stride_x;
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compute_confidence_hists_kernel_many_blocks<nthreads, nblocks><<<grid, threads>>>(
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img_win_width, img_block_width, win_block_stride_x, win_block_stride_y,
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block_hists, coefs, free_coef, threshold, confidences);
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cudaSafeCall(cudaThreadSynchronize());
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}
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template <int nthreads, // Number of threads per one histogram block
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int nblocks> // Number of histogram block processed by single GPU thread block
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int nblocks> // Number of histogram block processed by single GPU thread block
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__global__ void classify_hists_kernel_many_blocks(const int img_win_width, const int img_block_width,
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const int win_block_stride_x, const int win_block_stride_y,
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const float* block_hists, const float* coefs,
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@ -446,36 +415,8 @@ namespace cv { namespace gpu { namespace device
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__shared__ float products[nthreads * nblocks];
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const int tid = threadIdx.z * nthreads + threadIdx.x;
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products[tid] = product;
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__syncthreads();
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if (nthreads >= 512)
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{
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if (threadIdx.x < 256) products[tid] = product = product + products[tid + 256];
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__syncthreads();
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}
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if (nthreads >= 256)
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{
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if (threadIdx.x < 128) products[tid] = product = product + products[tid + 128];
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__syncthreads();
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}
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if (nthreads >= 128)
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{
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if (threadIdx.x < 64) products[tid] = product = product + products[tid + 64];
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__syncthreads();
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}
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if (threadIdx.x < 32)
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{
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volatile float* smem = products;
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if (nthreads >= 64) smem[tid] = product = product + smem[tid + 32];
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if (nthreads >= 32) smem[tid] = product = product + smem[tid + 16];
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if (nthreads >= 16) smem[tid] = product = product + smem[tid + 8];
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if (nthreads >= 8) smem[tid] = product = product + smem[tid + 4];
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if (nthreads >= 4) smem[tid] = product = product + smem[tid + 2];
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if (nthreads >= 2) smem[tid] = product = product + smem[tid + 1];
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}
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reduce<nthreads>(products, product, tid, plus<float>());
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if (threadIdx.x == 0)
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labels[blockIdx.y * img_win_width + blockIdx.x * blockDim.z + win_x] = (product + free_coef >= threshold);
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@ -868,4 +809,4 @@ namespace cv { namespace gpu { namespace device
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}}} // namespace cv { namespace gpu { namespace device
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#endif /* CUDA_DISABLER */
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#endif /* CUDA_DISABLER */
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