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Merge pull request #26396 from hanliutong:rvv-fp16-m2

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Use LMUL=2 in the RISC-V Vector (RVV) FP16 part. (5.x)
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Alexander Smorkalov 2024-11-02 13:30:31 +03:00 committed by GitHub
commit 55105719dd
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2 changed files with 432 additions and 472 deletions
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899
modules/core/include/opencv2/core/hal/intrin_rvv_scalable.hpp
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5
modules/core/src/matmul.simd.hpp
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@ -1595,7 +1595,10 @@ transform_16u( const ushort* src, ushort* dst, const float* m, int len, int scn,
static void
transform_32f( const float* src, float* dst, const float* m, int len, int scn, int dcn )
{
#if (CV_SIMD || CV_SIMD_SCALABLE) && !defined(__aarch64__) && !defined(_M_ARM64)
// Disabled for RISC-V Vector (scalable), because of:
// 1. v_matmuladd for RVV is 128-bit only but not scalable, this will fail the test `Core_Transform.accuracy`.
// 2. Both gcc and clang can autovectorize this, with better performance than using Universal intrinsic.
#if (CV_SIMD || CV_SIMD_SCALABLE) && !defined(__aarch64__) && !defined(_M_ARM64) && !(CV_TRY_RVV && CV_RVV)
int x = 0;
if( scn == 3 && dcn == 3 )
{