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Merge pull request #15738 from ChipKerchner:bugInt64x2Comparison
Fixing bug with comparison of v_int64x2 or v_uint64x2 * Casting v_uint64x2 to v_float64x2 and comparing does NOT work in all cases. Rewrite using epi64 instructions - faster too. * Fix bad merge. * Fix equal comparsion for non-SSE4.1. Add test cases for v_int64x2 comparisons. * Try to fix merge conflict. * Only test v_int64x2 comparisons if CV_SIMD_64F * Fix compiler warning.
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@ -1220,14 +1220,23 @@ inline _Tpvec operator >= (const _Tpvec& a, const _Tpvec& b) \
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OPENCV_HAL_IMPL_SSE_FLT_CMP_OP(v_float32x4, ps)
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OPENCV_HAL_IMPL_SSE_FLT_CMP_OP(v_float64x2, pd)
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#define OPENCV_HAL_IMPL_SSE_64BIT_CMP_OP(_Tpvec, cast) \
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#if CV_SSE4_1
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#define OPENCV_HAL_IMPL_SSE_64BIT_CMP_OP(_Tpvec) \
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inline _Tpvec operator == (const _Tpvec& a, const _Tpvec& b) \
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{ return cast(v_reinterpret_as_f64(a) == v_reinterpret_as_f64(b)); } \
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{ return _Tpvec(_mm_cmpeq_epi64(a.val, b.val)); } \
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inline _Tpvec operator != (const _Tpvec& a, const _Tpvec& b) \
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{ return cast(v_reinterpret_as_f64(a) != v_reinterpret_as_f64(b)); }
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{ return ~(a == b); }
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#else
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#define OPENCV_HAL_IMPL_SSE_64BIT_CMP_OP(_Tpvec) \
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inline _Tpvec operator == (const _Tpvec& a, const _Tpvec& b) \
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{ __m128i cmp = _mm_cmpeq_epi32(a.val, b.val); \
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return _Tpvec(_mm_and_si128(cmp, _mm_shuffle_epi32(cmp, _MM_SHUFFLE(2, 3, 0, 1)))); } \
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inline _Tpvec operator != (const _Tpvec& a, const _Tpvec& b) \
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{ return ~(a == b); }
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#endif
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OPENCV_HAL_IMPL_SSE_64BIT_CMP_OP(v_uint64x2, v_reinterpret_as_u64)
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OPENCV_HAL_IMPL_SSE_64BIT_CMP_OP(v_int64x2, v_reinterpret_as_s64)
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OPENCV_HAL_IMPL_SSE_64BIT_CMP_OP(v_uint64x2)
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OPENCV_HAL_IMPL_SSE_64BIT_CMP_OP(v_int64x2)
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inline v_float32x4 v_not_nan(const v_float32x4& a)
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{ return v_float32x4(_mm_cmpord_ps(a.val, a.val)); }
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@ -1442,6 +1442,50 @@ template<typename R> struct TheTest
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return *this;
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}
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#endif
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#if CV_SIMD_64F
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TheTest & test_cmp64()
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{
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Data<R> dataA, dataB;
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R a = dataA, b = dataB;
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for (int i = 0; i < R::nlanes; ++i)
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{
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dataA[i] = dataB[i];
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}
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dataA[0]++;
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a = dataA, b = dataB;
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Data<R> resC = (a == b);
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Data<R> resD = (a != b);
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for (int i = 0; i < R::nlanes; ++i)
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{
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SCOPED_TRACE(cv::format("i=%d", i));
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EXPECT_EQ(dataA[i] == dataB[i], resC[i] != 0);
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EXPECT_EQ(dataA[i] != dataB[i], resD[i] != 0);
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}
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for (int i = 0; i < R::nlanes; ++i)
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{
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dataA[i] = dataB[i] = (LaneType)-1;
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}
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a = dataA, b = dataB;
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resC = (a == b);
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resD = (a != b);
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for (int i = 0; i < R::nlanes; ++i)
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{
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SCOPED_TRACE(cv::format("i=%d", i));
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EXPECT_EQ(dataA[i] == dataB[i], resC[i] != 0);
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EXPECT_EQ(dataA[i] != dataB[i], resD[i] != 0);
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}
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return *this;
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}
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#endif
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};
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@ -1657,6 +1701,9 @@ void test_hal_intrin_uint64()
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TheTest<v_uint64>()
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.test_loadstore()
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.test_addsub()
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#if CV_SIMD_64F
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.test_cmp64()
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#endif
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.test_shift<1>().test_shift<8>()
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.test_logic()
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.test_reverse()
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@ -1671,6 +1718,9 @@ void test_hal_intrin_int64()
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TheTest<v_int64>()
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.test_loadstore()
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.test_addsub()
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#if CV_SIMD_64F
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.test_cmp64()
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#endif
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.test_shift<1>().test_shift<8>()
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.test_logic()
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.test_reverse()
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