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Merge pull request #19486 from fpetrogalli:dotprod_fast-3.4
* [hal][neon] Optimize the v_dotprod_fast intrinsics for aarch64. On Armv8 in AArch64 execution mode, we can skip the sequence v<op>_<ty>(vget_high_<ty>(x), vget_high_<ty>(y)) in favour of v<op>_high_<ty>(x, y) This has better changes for recent compilers to use less data movement operations and better register allocation. See for example: https://godbolt.org/z/bPq7vd * [hal][neon] Fix build failure on armv7. * [hal][neon] Address review comments in PR. PR: https://github.com/opencv/opencv/pull/19486 * [hal][neon] Define macro to check for the AArch64 execution state of Armv8. * [hal][neon] Fix macro definition for AArch64. The fix is needed to prevent warnings when building for Armv7.
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@ -62,6 +62,22 @@ CV_CPU_OPTIMIZATION_HAL_NAMESPACE_BEGIN
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#define CV_SIMD128_64F 0
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#endif
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// The following macro checks if the code is being compiled for the
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// AArch64 execution state of Armv8, to enable the 128-bit
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// intrinsics. The macro `__ARM_64BIT_STATE` is the one recommended by
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// the Arm C Language Extension (ACLE) specifications [1] to check the
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// availability of 128-bit intrinsics, and it is supporrted by clang
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// and gcc. The macro `_M_ARM64` is the equivalent one for Microsoft
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// Visual Studio [2] .
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//
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// [1] https://developer.arm.com/documentation/101028/0012/13--Advanced-SIMD--Neon--intrinsics
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// [2] https://docs.microsoft.com/en-us/cpp/preprocessor/predefined-macros
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#if defined(__ARM_64BIT_STATE) || defined(_M_ARM64)
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#define CV_NEON_AARCH64 1
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#else
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#define CV_NEON_AARCH64 0
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#endif
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// TODO
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#define CV_NEON_DOT 0
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@ -726,41 +742,61 @@ inline v_float64x2 v_dotprod_expand(const v_int32x4& a, const v_int32x4& b,
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// 16 >> 32
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inline v_int32x4 v_dotprod_fast(const v_int16x8& a, const v_int16x8& b)
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{
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#if CV_NEON_AARCH64
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int32x4_t p = vmull_s16(vget_low_s16(a.val), vget_low_s16(b.val));
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return v_int32x4(vmlal_high_s16(p, a.val, b.val));
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#else
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int16x4_t a0 = vget_low_s16(a.val);
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int16x4_t a1 = vget_high_s16(a.val);
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int16x4_t b0 = vget_low_s16(b.val);
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int16x4_t b1 = vget_high_s16(b.val);
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int32x4_t p = vmull_s16(a0, b0);
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return v_int32x4(vmlal_s16(p, a1, b1));
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#endif
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}
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inline v_int32x4 v_dotprod_fast(const v_int16x8& a, const v_int16x8& b, const v_int32x4& c)
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{
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#if CV_NEON_AARCH64
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int32x4_t p = vmlal_s16(c.val, vget_low_s16(a.val), vget_low_s16(b.val));
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return v_int32x4(vmlal_high_s16(p, a.val, b.val));
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#else
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int16x4_t a0 = vget_low_s16(a.val);
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int16x4_t a1 = vget_high_s16(a.val);
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int16x4_t b0 = vget_low_s16(b.val);
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int16x4_t b1 = vget_high_s16(b.val);
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int32x4_t p = vmlal_s16(c.val, a0, b0);
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return v_int32x4(vmlal_s16(p, a1, b1));
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#endif
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}
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// 32 >> 64
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inline v_int64x2 v_dotprod_fast(const v_int32x4& a, const v_int32x4& b)
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{
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#if CV_NEON_AARCH64
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int64x2_t p = vmull_s32(vget_low_s32(a.val), vget_low_s32(b.val));
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return v_int64x2(vmlal_high_s32(p, a.val, b.val));
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#else
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int32x2_t a0 = vget_low_s32(a.val);
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int32x2_t a1 = vget_high_s32(a.val);
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int32x2_t b0 = vget_low_s32(b.val);
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int32x2_t b1 = vget_high_s32(b.val);
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int64x2_t p = vmull_s32(a0, b0);
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return v_int64x2(vmlal_s32(p, a1, b1));
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#endif
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}
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inline v_int64x2 v_dotprod_fast(const v_int32x4& a, const v_int32x4& b, const v_int64x2& c)
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{
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#if CV_NEON_AARCH64
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int64x2_t p = vmlal_s32(c.val, vget_low_s32(a.val), vget_low_s32(b.val));
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return v_int64x2(vmlal_high_s32(p, a.val, b.val));
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#else
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int32x2_t a0 = vget_low_s32(a.val);
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int32x2_t a1 = vget_high_s32(a.val);
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int32x2_t b0 = vget_low_s32(b.val);
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int32x2_t b1 = vget_high_s32(b.val);
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int64x2_t p = vmlal_s32(c.val, a0, b0);
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return v_int64x2(vmlal_s32(p, a1, b1));
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#endif
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}
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// 8 >> 32
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@ -1292,7 +1328,7 @@ inline int64 v_reduce_sum(const v_int64x2& a)
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#if CV_SIMD128_64F
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inline double v_reduce_sum(const v_float64x2& a)
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{
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return vgetq_lane_f64(a.val, 0) + vgetq_lane_f64(a.val, 1);
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return vaddvq_f64(a.val);
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}
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#endif
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