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Merge pull request #26029 from fengyuentau:dnn/fix_cuda_matmul_crash
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78630ddc67
@ -425,8 +425,8 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl { namespace cu
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const auto batch_count = static_cast<int>(batchCount);
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AutoBuffer<half> buffer(3 * batch_count);
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auto A_slices = (half**)(buffer.data());
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AutoBuffer<half*> buffer(3 * batch_count);
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auto A_slices = buffer.data();
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auto B_slices = A_slices + batch_count;
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auto C_slices = B_slices + batch_count;
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// collect A, B and C slices
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@ -438,18 +438,18 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl { namespace cu
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const half **dev_A_slices = 0, **dev_B_slices = 0;
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half **dev_C_slices = 0;
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cudaMalloc((void**)&dev_A_slices, batch_count * sizeof(half*));
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cudaMalloc((void**)&dev_B_slices, batch_count * sizeof(half*));
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cudaMalloc((void**)&dev_C_slices, batch_count * sizeof(half*));
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cudaMemcpy(dev_A_slices, A_slices, batch_count * sizeof(half*), cudaMemcpyHostToDevice);
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cudaMemcpy(dev_B_slices, B_slices, batch_count * sizeof(half*), cudaMemcpyHostToDevice);
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cudaMemcpy(dev_C_slices, C_slices, batch_count * sizeof(half*), cudaMemcpyHostToDevice);
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CUDA4DNN_CHECK_CUDA(cudaMalloc((void**)&dev_A_slices, batch_count * sizeof(half*)));
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CUDA4DNN_CHECK_CUDA(cudaMalloc((void**)&dev_B_slices, batch_count * sizeof(half*)));
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CUDA4DNN_CHECK_CUDA(cudaMalloc((void**)&dev_C_slices, batch_count * sizeof(half*)));
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CUDA4DNN_CHECK_CUDA(cudaMemcpy(dev_A_slices, A_slices, batch_count * sizeof(half*), cudaMemcpyHostToDevice));
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CUDA4DNN_CHECK_CUDA(cudaMemcpy(dev_B_slices, B_slices, batch_count * sizeof(half*), cudaMemcpyHostToDevice));
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CUDA4DNN_CHECK_CUDA(cudaMemcpy(dev_C_slices, C_slices, batch_count * sizeof(half*), cudaMemcpyHostToDevice));
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CUDA4DNN_CHECK_CUBLAS(cublasHgemmBatched(handle.get(), opa, opb, iM, iN, iK, &alpha, dev_A_slices, ilda, dev_B_slices, ildb, &beta, dev_C_slices, ildc, batch_count));
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cudaFree(dev_A_slices);
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cudaFree(dev_B_slices);
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cudaFree(dev_C_slices);
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CUDA4DNN_CHECK_CUDA(cudaFree(dev_A_slices));
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CUDA4DNN_CHECK_CUDA(cudaFree(dev_B_slices));
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CUDA4DNN_CHECK_CUDA(cudaFree(dev_C_slices));
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}
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template <> inline
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@ -475,8 +475,8 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl { namespace cu
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const auto batch_count = static_cast<int>(batchCount);
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AutoBuffer<float> buffer(3 * batch_count);
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auto A_slices = (float**)(buffer.data());
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AutoBuffer<float*> buffer(3 * batch_count);
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auto A_slices = buffer.data();
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auto B_slices = A_slices + batch_count;
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auto C_slices = B_slices + batch_count;
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// collect A, B and C slices
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@ -488,19 +488,19 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl { namespace cu
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const float **dev_A_slices = 0, **dev_B_slices = 0;
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float **dev_C_slices = 0;
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cudaMalloc((void**)&dev_A_slices, batch_count * sizeof(float*));
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cudaMalloc((void**)&dev_B_slices, batch_count * sizeof(float*));
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cudaMalloc((void**)&dev_C_slices, batch_count * sizeof(float*));
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cudaMemcpy(dev_A_slices, A_slices, batch_count * sizeof(float*), cudaMemcpyHostToDevice);
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cudaMemcpy(dev_B_slices, B_slices, batch_count * sizeof(float*), cudaMemcpyHostToDevice);
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cudaMemcpy(dev_C_slices, C_slices, batch_count * sizeof(float*), cudaMemcpyHostToDevice);
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CUDA4DNN_CHECK_CUDA(cudaMalloc((void**)&dev_A_slices, batch_count * sizeof(float*)));
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CUDA4DNN_CHECK_CUDA(cudaMalloc((void**)&dev_B_slices, batch_count * sizeof(float*)));
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CUDA4DNN_CHECK_CUDA(cudaMalloc((void**)&dev_C_slices, batch_count * sizeof(float*)));
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CUDA4DNN_CHECK_CUDA(cudaMemcpy(dev_A_slices, A_slices, batch_count * sizeof(float*), cudaMemcpyHostToDevice));
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CUDA4DNN_CHECK_CUDA(cudaMemcpy(dev_B_slices, B_slices, batch_count * sizeof(float*), cudaMemcpyHostToDevice));
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CUDA4DNN_CHECK_CUDA(cudaMemcpy(dev_C_slices, C_slices, batch_count * sizeof(float*), cudaMemcpyHostToDevice));
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// cuBLAS is column-major
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CUDA4DNN_CHECK_CUBLAS(cublasSgemmBatched(handle.get(), opa, opb, iM, iN, iK, &alpha, dev_A_slices, ilda, dev_B_slices, ildb, &beta, dev_C_slices, ildc, batch_count));
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cudaFree(dev_A_slices);
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cudaFree(dev_B_slices);
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cudaFree(dev_C_slices);
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CUDA4DNN_CHECK_CUDA(cudaFree(dev_A_slices));
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CUDA4DNN_CHECK_CUDA(cudaFree(dev_B_slices));
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CUDA4DNN_CHECK_CUDA(cudaFree(dev_C_slices));
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}
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}}}}} /* namespace cv::dnn::cuda4dnn::csl::cublas */
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@ -1002,6 +1002,10 @@ TEST_P(Test_ONNX_layers, MatMul_init_bcast)
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testONNXModels("matmul_init_bcast");
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}
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TEST_P(Test_ONNX_layers, MatMul_bcast_3dx2d) {
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testONNXModels("matmul_bcast");
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}
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TEST_P(Test_ONNX_layers, MatMulAdd)
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{
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#if defined(INF_ENGINE_RELEASE) && INF_ENGINE_VER_MAJOR_EQ(2022010000)
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