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avx2
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28833421ae
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@ -221,6 +221,7 @@ OCV_OPTION(ENABLE_SSSE3 "Enable SSSE3 instructions"
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OCV_OPTION(ENABLE_SSE41 "Enable SSE4.1 instructions" OFF IF ((CV_ICC OR CMAKE_COMPILER_IS_GNUCXX) AND (X86 OR X86_64)) )
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OCV_OPTION(ENABLE_SSE42 "Enable SSE4.2 instructions" OFF IF (CMAKE_COMPILER_IS_GNUCXX AND (X86 OR X86_64)) )
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OCV_OPTION(ENABLE_AVX "Enable AVX instructions" OFF IF ((MSVC OR CMAKE_COMPILER_IS_GNUCXX) AND (X86 OR X86_64)) )
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OCV_OPTION(ENABLE_AVX2 "Enable AVX2 instructions" OFF IF ((MSVC OR CMAKE_COMPILER_IS_GNUCXX) AND (X86 OR X86_64)) )
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OCV_OPTION(ENABLE_NEON "Enable NEON instructions" OFF IF CMAKE_COMPILER_IS_GNUCXX AND (ARM OR IOS) )
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OCV_OPTION(ENABLE_VFPV3 "Enable VFPv3-D32 instructions" OFF IF CMAKE_COMPILER_IS_GNUCXX AND (ARM OR IOS) )
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OCV_OPTION(ENABLE_NOISY_WARNINGS "Show all warnings even if they are too noisy" OFF )
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@ -140,6 +140,9 @@ if(CMAKE_COMPILER_IS_GNUCXX)
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if(ENABLE_AVX)
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add_extra_compiler_option(-mavx)
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endif()
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if(ENABLE_AVX2)
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add_extra_compiler_option(-mavx2)
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endif()
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# GCC depresses SSEx instructions when -mavx is used. Instead, it generates new AVX instructions or AVX equivalence for all SSEx instructions when needed.
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if(NOT OPENCV_EXTRA_CXX_FLAGS MATCHES "-mavx")
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@ -114,7 +114,8 @@
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#define CV_CPU_SSE4_2 7
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#define CV_CPU_POPCNT 8
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#define CV_CPU_AVX 10
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#define CV_CPU_NEON 11
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#define CV_CPU_AVX2 11
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#define CV_CPU_NEON 12
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// when adding to this list remember to update the enum in core/utility.cpp
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#define CV_HARDWARE_MAX_FEATURE 255
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@ -141,7 +142,7 @@
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# include <nmmintrin.h>
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# define CV_SSE4_2 1
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# endif
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# if defined __AVX__ || (defined _MSC_FULL_VER && _MSC_FULL_VER >= 160040219)
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# if defined __AVX__ || defined __AVX2__ || (defined _MSC_FULL_VER && _MSC_FULL_VER >= 160040219)
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// MS Visual Studio 2010 (2012?) has no macro pre-defined to identify the use of /arch:AVX
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// See: http://connect.microsoft.com/VisualStudio/feedback/details/605858/arch-avx-should-define-a-predefined-macro-in-x64-and-set-a-unique-value-for-m-ix86-fp-in-win32
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# include <immintrin.h>
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@ -150,6 +151,9 @@
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# define __xgetbv() _xgetbv(_XCR_XFEATURE_ENABLED_MASK)
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# else
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# define __xgetbv() 0
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# ifdef __AVX2__
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# define CV_AVX2 1
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# endif
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# endif
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# endif
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#endif
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@ -187,6 +191,9 @@
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#ifndef CV_AVX
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# define CV_AVX 0
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#endif
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#ifndef CV_AVX2
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# define CV_AVX2 0
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#endif
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#ifndef CV_NEON
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# define CV_NEON 0
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#endif
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@ -2294,6 +2294,24 @@ cvtScale_<short, int, float>( const short* src, size_t sstep,
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{
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int x = 0;
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#if CV_AVX2
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if (USE_AVX2)
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{
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__m256 scale256 = _mm256_set1_ps (scale);
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__m256 shift256 = _mm256_set1_ps (shift);
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__m256i zero = _mm256_setzero_si256();
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for ( ; x <= size.width - 16; x += 16)
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{
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__m256i v_src = _mm256_loadu_si256((__m256i const *)(src + x));
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__m256i v_src_lo = _mm256_unpacklo_epi16(v_src, zero);
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__m256i v_src_hi = _mm256_unpackhi_epi16(v_src, zero);
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__m256 v_dst0 = _mm256_add_ps( _mm256_mul_ps(_mm256_cvtepi32_ps (v_src_lo), scale256), shift256);
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__m256 v_dst1 = _mm256_add_ps( _mm256_mul_ps(_mm256_cvtepi32_ps (v_src_hi), scale256), shift256);
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_mm256_storeu_si256 ((__m256i *)(dst + x), _mm256_cvtps_epi32(v_dst0));
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_mm256_storeu_si256 ((__m256i *)(dst + x + 8), _mm256_cvtps_epi32(v_dst1));
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}
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}
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#endif
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#if CV_SSE2
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if (USE_SSE2)//~5X
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{
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@ -2330,24 +2348,6 @@ cvtScale_<short, int, float>( const short* src, size_t sstep,
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}
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#endif
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//We will wait Haswell
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/*
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#if CV_AVX
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if(USE_AVX)//2X - bad variant
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{
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////TODO:AVX implementation (optimization?) required
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__m256 scale256 = _mm256_set1_ps (scale);
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__m256 shift256 = _mm256_set1_ps (shift);
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for(; x <= size.width - 8; x += 8 )
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{
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__m256i buf = _mm256_set_epi32((int)(*(src+x+7)),(int)(*(src+x+6)),(int)(*(src+x+5)),(int)(*(src+x+4)),(int)(*(src+x+3)),(int)(*(src+x+2)),(int)(*(src+x+1)),(int)(*(src+x)));
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__m256 r0 = _mm256_add_ps( _mm256_mul_ps(_mm256_cvtepi32_ps (buf), scale256), shift256);
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__m256i res = _mm256_cvtps_epi32(r0);
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_mm256_storeu_si256 ((__m256i*)(dst+x), res);
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}
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}
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#endif*/
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for(; x < size.width; x++ )
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dst[x] = saturate_cast<int>(src[x]*scale + shift);
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}
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@ -192,6 +192,7 @@ struct NoVec
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extern volatile bool USE_SSE2;
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extern volatile bool USE_SSE4_2;
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extern volatile bool USE_AVX;
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extern volatile bool USE_AVX2;
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enum { BLOCK_SIZE = 1024 };
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@ -82,6 +82,22 @@
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pop ebx
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}
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}
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static void __cpuidex(int* cpuid_data, int, int)
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{
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__asm
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{
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push edi
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mov edi, cpuid_data
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mov eax, 7
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mov ecx, 0
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cpuid
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mov [edi], eax
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mov [edi + 4], ebx
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mov [edi + 8], ecx
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mov [edi + 12], edx
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pop edi
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}
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}
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#endif
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#endif
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@ -251,6 +267,40 @@ struct HWFeatures
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f.have[CV_CPU_SSE4_2] = (cpuid_data[2] & (1<<20)) != 0;
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f.have[CV_CPU_POPCNT] = (cpuid_data[2] & (1<<23)) != 0;
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f.have[CV_CPU_AVX] = (((cpuid_data[2] & (1<<28)) != 0)&&((cpuid_data[2] & (1<<27)) != 0));//OS uses XSAVE_XRSTORE and CPU support AVX
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// make the second call to the cpuid command in order to get
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// information about extended features like AVX2
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#if defined _MSC_VER && (defined _M_IX86 || defined _M_X64)
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__cpuidex(cpuid_data, 7, 0);
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#elif defined __GNUC__ && (defined __i386__ || defined __x86_64__)
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#ifdef __x86_64__
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asm __volatile__
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(
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"movl $7, %%eax\n\t"
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"movl $0, %%ecx\n\t"
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"cpuid\n\t"
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:[eax]"=a"(cpuid_data[0]),[ebx]"=b"(cpuid_data[1]),[ecx]"=c"(cpuid_data[2]),[edx]"=d"(cpuid_data[3])
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:
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: "cc"
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);
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#else
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asm volatile
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(
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"pushl %%eax\n\t"
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"pushl %%edx\n\t"
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"movl $7,%%eax\n\t"
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"movl $0,%%ecx\n\t"
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"cpuid\n\t"
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"popl %%edx\n\t"
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"popl %%eax\n\t"
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: "=b"(cpuid_data[1]), "=c"(cpuid_data[2])
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:
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: "cc"
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);
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#endif
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#endif
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f.have[CV_CPU_AVX2] = (cpuid_data[1] & (1<<5)) != 0;
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}
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return f;
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@ -290,6 +340,7 @@ IPPInitializer ippInitializer;
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volatile bool USE_SSE2 = featuresEnabled.have[CV_CPU_SSE2];
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volatile bool USE_SSE4_2 = featuresEnabled.have[CV_CPU_SSE4_2];
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volatile bool USE_AVX = featuresEnabled.have[CV_CPU_AVX];
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volatile bool USE_AVX2 = featuresEnabled.have[CV_CPU_AVX2];
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void setUseOptimized( bool flag )
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{
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@ -3019,6 +3019,9 @@ void printVersionInfo(bool useStdOut)
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#if CV_AVX
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if (checkHardwareSupport(CV_CPU_AVX)) cpu_features += " avx";
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#endif
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#if CV_AVX2
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if (checkHardwareSupport(CV_CPU_AVX2)) cpu_features += " avx2";
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#endif
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#if CV_NEON
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cpu_features += " neon"; // NEON is currently not checked at runtime
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#endif
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