mirror of
https://github.com/opencv/opencv.git
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update convertFp16 using CV_CPU_CALL_FP16
* avoid link error (move the implementation of software version to header) * make getConvertFuncFp16 local (move from precomp.hpp to convert.hpp) * fix error on 32bit x86
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@ -44,7 +44,7 @@
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#include "precomp.hpp"
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#include "opencl_kernels_core.hpp"
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#include "opencv2/core/hal/intrin.hpp"
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#include "convert.hpp"
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#include "opencv2/core/openvx/ovx_defs.hpp"
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@ -4573,256 +4573,40 @@ struct Cvt_SIMD<float, int>
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#endif
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#if !CV_FP16_TYPE
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// const numbers for floating points format
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const unsigned int kShiftSignificand = 13;
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const unsigned int kMaskFp16Significand = 0x3ff;
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const unsigned int kBiasFp16Exponent = 15;
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const unsigned int kBiasFp32Exponent = 127;
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#endif
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#if CV_FP16_TYPE
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static float convertFp16SW(short fp16)
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{
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// Fp16 -> Fp32
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Cv16suf a;
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a.i = fp16;
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return (float)a.h;
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}
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#else
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static float convertFp16SW(short fp16)
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{
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// Fp16 -> Fp32
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Cv16suf b;
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b.i = fp16;
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int exponent = b.fmt.exponent - kBiasFp16Exponent;
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int significand = b.fmt.significand;
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Cv32suf a;
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a.i = 0;
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a.fmt.sign = b.fmt.sign; // sign bit
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if( exponent == 16 )
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{
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// Inf or NaN
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a.i = a.i | 0x7F800000;
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if( significand != 0 )
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{
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// NaN
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#if defined(__x86_64__) || defined(_M_X64)
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// 64bit
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a.i = a.i | 0x7FC00000;
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#endif
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a.fmt.significand = a.fmt.significand | (significand << kShiftSignificand);
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}
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return a.f;
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}
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else if ( exponent == -15 )
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{
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// subnormal in Fp16
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if( significand == 0 )
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{
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// zero
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return a.f;
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}
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else
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{
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int shift = -1;
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while( ( significand & 0x400 ) == 0 )
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{
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significand = significand << 1;
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shift++;
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}
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significand = significand & kMaskFp16Significand;
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exponent -= shift;
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}
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}
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a.fmt.exponent = (exponent+kBiasFp32Exponent);
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a.fmt.significand = significand << kShiftSignificand;
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return a.f;
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}
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#endif
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#if CV_FP16_TYPE
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static short convertFp16SW(float fp32)
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{
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// Fp32 -> Fp16
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Cv16suf a;
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a.h = (__fp16)fp32;
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return a.i;
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}
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#else
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static short convertFp16SW(float fp32)
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{
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// Fp32 -> Fp16
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Cv32suf a;
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a.f = fp32;
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int exponent = a.fmt.exponent - kBiasFp32Exponent;
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int significand = a.fmt.significand;
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Cv16suf result;
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result.i = 0;
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unsigned int absolute = a.i & 0x7fffffff;
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if( 0x477ff000 <= absolute )
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{
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// Inf in Fp16
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result.i = result.i | 0x7C00;
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if( exponent == 128 && significand != 0 )
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{
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// NaN
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result.i = (short)( result.i | 0x200 | ( significand >> kShiftSignificand ) );
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}
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}
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else if ( absolute < 0x33000001 )
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{
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// too small for fp16
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result.i = 0;
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}
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else if ( absolute < 0x33c00000 )
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{
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result.i = 1;
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}
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else if ( absolute < 0x34200001 )
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{
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result.i = 2;
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}
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else if ( absolute < 0x387fe000 )
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{
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// subnormal in Fp16
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int fp16Significand = significand | 0x800000;
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int bitShift = (-exponent) - 1;
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fp16Significand = fp16Significand >> bitShift;
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// special cases to round up
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bitShift = exponent + 24;
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int threshold = ( ( 0x400000 >> bitShift ) | ( ( ( significand & ( 0x800000 >> bitShift ) ) >> ( 126 - a.fmt.exponent ) ) ^ 1 ) );
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if( threshold <= ( significand & ( 0xffffff >> ( exponent + 25 ) ) ) )
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{
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fp16Significand++;
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}
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result.i = (short)fp16Significand;
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}
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else
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{
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// usual situation
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// exponent
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result.fmt.exponent = ( exponent + kBiasFp16Exponent );
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// significand;
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short fp16Significand = (short)(significand >> kShiftSignificand);
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result.fmt.significand = fp16Significand;
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// special cases to round up
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short lsb10bitsFp32 = (significand & 0x1fff);
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short threshold = 0x1000 + ( ( fp16Significand & 0x1 ) ? 0 : 1 );
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if( threshold <= lsb10bitsFp32 )
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{
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result.i++;
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}
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else if ( fp16Significand == 0x3ff && exponent == -15)
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{
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result.i++;
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}
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}
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// sign bit
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result.fmt.sign = a.fmt.sign;
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return result.i;
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}
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#endif
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// template for FP16 HW conversion function
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template<typename T, typename DT> static void
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cvtScaleHalf_( const T* src, size_t sstep, DT* dst, size_t dstep, Size size);
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template<> void
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cvtScaleHalf_<float, short>( const float* src, size_t sstep, short* dst, size_t dstep, Size size)
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cvtScaleHalf_<float, short>( const float* src, size_t sstep, short* dst, size_t dstep, Size size )
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{
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CV_CPU_CALL_FP16(cvtScaleHalf_SIMD32f16f, (src, sstep, dst, dstep, size));
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sstep /= sizeof(src[0]);
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dstep /= sizeof(dst[0]);
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if( checkHardwareSupport(CV_CPU_FP16) )
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for( ; size.height--; src += sstep, dst += dstep )
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{
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for( ; size.height--; src += sstep, dst += dstep )
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for ( int x = 0; x < size.width; x++ )
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{
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int x = 0;
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#if defined(__x86_64__) || defined(_M_X64) || defined(_M_IX86) || defined(i386)
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if ( ( (intptr_t)dst & 0xf ) == 0 )
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#endif
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{
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#if CV_FP16 && CV_SIMD128
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for ( ; x <= size.width - 4; x += 4)
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{
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v_float32x4 v_src = v_load(src + x);
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v_float16x4 v_dst = v_cvt_f16(v_src);
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v_store_f16(dst + x, v_dst);
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}
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#endif
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}
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for ( ; x < size.width; x++ )
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{
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dst[x] = convertFp16SW(src[x]);
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}
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}
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}
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else
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{
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for( ; size.height--; src += sstep, dst += dstep )
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{
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int x = 0;
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for ( ; x < size.width; x++ )
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{
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dst[x] = convertFp16SW(src[x]);
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}
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dst[x] = convertFp16SW(src[x]);
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}
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}
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}
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template<> void
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cvtScaleHalf_<short, float>( const short* src, size_t sstep, float* dst, size_t dstep, Size size)
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cvtScaleHalf_<short, float>( const short* src, size_t sstep, float* dst, size_t dstep, Size size )
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{
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CV_CPU_CALL_FP16(cvtScaleHalf_SIMD16f32f, (src, sstep, dst, dstep, size));
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sstep /= sizeof(src[0]);
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dstep /= sizeof(dst[0]);
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if( checkHardwareSupport(CV_CPU_FP16) )
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for( ; size.height--; src += sstep, dst += dstep )
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{
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for( ; size.height--; src += sstep, dst += dstep )
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for ( int x = 0; x < size.width; x++ )
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{
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int x = 0;
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#if defined(__x86_64__) || defined(_M_X64) || defined(_M_IX86) || defined(i386)
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if ( ( (intptr_t)src & 0xf ) == 0 )
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#endif
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{
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#if CV_FP16 && CV_SIMD128
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for ( ; x <= size.width - 4; x += 4)
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{
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v_float16x4 v_src = v_load_f16(src + x);
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v_float32x4 v_dst = v_cvt_f32(v_src);
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v_store(dst + x, v_dst);
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}
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#endif
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}
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for ( ; x < size.width; x++ )
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{
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dst[x] = convertFp16SW(src[x]);
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}
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}
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}
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else
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{
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for( ; size.height--; src += sstep, dst += dstep )
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{
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int x = 0;
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for ( ; x < size.width; x++ )
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{
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dst[x] = convertFp16SW(src[x]);
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}
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dst[x] = convertFp16SW(src[x]);
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}
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}
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}
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@ -5024,12 +4808,13 @@ static void cvtScaleAbs##suffix( const stype* src, size_t sstep, const uchar*, s
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}
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#define DEF_CVT_SCALE_FP16_FUNC(suffix, stype, dtype) \
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static void cvtScaleHalf##suffix( const stype* src, size_t sstep, const uchar*, size_t, \
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dtype* dst, size_t dstep, Size size, double*) \
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static void cvtScaleHalf##suffix( const stype* src, size_t sstep, \
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dtype* dst, size_t dstep, Size size) \
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{ \
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cvtScaleHalf_<stype,dtype>(src, sstep, dst, dstep, size); \
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}
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#define DEF_CVT_SCALE_FUNC(suffix, stype, dtype, wtype) \
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static void cvtScale##suffix( const stype* src, size_t sstep, const uchar*, size_t, \
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dtype* dst, size_t dstep, Size size, double* scale) \
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@ -5210,12 +4995,16 @@ static BinaryFunc getCvtScaleAbsFunc(int depth)
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return cvtScaleAbsTab[depth];
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}
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BinaryFunc getConvertFuncFp16(int ddepth)
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typedef void (*UnaryFunc)(const uchar* src1, size_t step1,
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uchar* dst, size_t step, Size sz,
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void*);
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static UnaryFunc getConvertFuncFp16(int ddepth)
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{
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static BinaryFunc cvtTab[] =
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static UnaryFunc cvtTab[] =
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{
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0, 0, 0,
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(BinaryFunc)(cvtScaleHalf32f16f), 0, (BinaryFunc)(cvtScaleHalf16f32f),
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(UnaryFunc)(cvtScaleHalf32f16f), 0, (UnaryFunc)(cvtScaleHalf16f32f),
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0, 0,
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};
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return cvtTab[CV_MAT_DEPTH(ddepth)];
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@ -5461,14 +5250,14 @@ void cv::convertFp16( InputArray _src, OutputArray _dst)
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int type = CV_MAKETYPE(ddepth, src.channels());
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_dst.create( src.dims, src.size, type );
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Mat dst = _dst.getMat();
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BinaryFunc func = getConvertFuncFp16(ddepth);
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UnaryFunc func = getConvertFuncFp16(ddepth);
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int cn = src.channels();
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CV_Assert( func != 0 );
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if( src.dims <= 2 )
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{
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Size sz = getContinuousSize(src, dst, cn);
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func( src.data, src.step, 0, 0, dst.data, dst.step, sz, 0);
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func( src.data, src.step, dst.data, dst.step, sz, 0);
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}
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else
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{
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@ -5478,7 +5267,7 @@ void cv::convertFp16( InputArray _src, OutputArray _dst)
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Size sz((int)(it.size*cn), 1);
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for( size_t i = 0; i < it.nplanes; i++, ++it )
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func(ptrs[0], 1, 0, 0, ptrs[1], 1, sz, 0);
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func(ptrs[0], 1, ptrs[1], 1, sz, 0);
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}
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}
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modules/core/src/convert.fp16.cpp
Normal file
172
modules/core/src/convert.fp16.cpp
Normal file
@ -0,0 +1,172 @@
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/*M///////////////////////////////////////////////////////////////////////////////////////
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//
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// IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.
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//
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// By downloading, copying, installing or using the software you agree to this license.
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// If you do not agree to this license, do not download, install,
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// copy or use the software.
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//
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//
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// License Agreement
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// For Open Source Computer Vision Library
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//
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// Copyright (C) 2000-2008, Intel Corporation, all rights reserved.
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// Copyright (C) 2009-2011, Willow Garage Inc., all rights reserved.
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// Copyright (C) 2014-2015, Itseez Inc., all rights reserved.
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// Third party copyrights are property of their respective owners.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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//
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// * Redistribution's of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// * Redistribution's in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// * The name of the copyright holders may not be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// This software is provided by the copyright holders and contributors "as is" and
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// any express or implied warranties, including, but not limited to, the implied
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// warranties of merchantability and fitness for a particular purpose are disclaimed.
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// In no event shall the Intel Corporation or contributors be liable for any direct,
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// indirect, incidental, special, exemplary, or consequential damages
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// (including, but not limited to, procurement of substitute goods or services;
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// loss of use, data, or profits; or business interruption) however caused
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// and on any theory of liability, whether in contract, strict liability,
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// or tort (including negligence or otherwise) arising in any way out of
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// the use of this software, even if advised of the possibility of such damage.
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//
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//M*/
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#include "precomp.hpp"
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#include "convert.hpp"
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namespace cv
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{
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namespace opt_FP16
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{
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#if !defined(CV_NEON) || !CV_NEON
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const static int cVectorWidth = 8;
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void cvtScaleHalf_SIMD32f16f( const float* src, size_t sstep, short* dst, size_t dstep, cv::Size size )
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{
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CV_INSTRUMENT_REGION()
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sstep /= sizeof(src[0]);
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dstep /= sizeof(dst[0]);
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for( ; size.height--; src += sstep, dst += dstep )
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{
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int x = 0;
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for ( ; x <= size.width - cVectorWidth ; x += cVectorWidth )
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{
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__m256 v_src = _mm256_loadu_ps(src + x);
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// round to nearest even
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__m128i v_dst = _mm256_cvtps_ph(v_src, 0);
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_mm_storeu_si128((__m128i*)(dst + x), v_dst);
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}
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for ( ; x < size.width; x++ )
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{
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dst[x] = convertFp16SW(src[x]);
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}
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}
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}
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void cvtScaleHalf_SIMD16f32f( const short* src, size_t sstep, float* dst, size_t dstep, cv::Size size )
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{
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CV_INSTRUMENT_REGION()
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sstep /= sizeof(src[0]);
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dstep /= sizeof(dst[0]);
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for( ; size.height--; src += sstep, dst += dstep )
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{
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int x = 0;
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for ( ; x <= size.width - cVectorWidth ; x += cVectorWidth )
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{
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__m128i v_src = _mm_loadu_si128((__m128i*)(src + x));
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__m256 v_dst = _mm256_cvtph_ps(v_src);
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_mm256_storeu_ps(dst + x, v_dst);
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}
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for ( ; x < size.width; x++ )
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{
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dst[x] = convertFp16SW(src[x]);
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}
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}
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}
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#elif CV_NEON
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const static int cVectorWidth = 4;
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template <typename T> static inline float16x4_t vld1_f16(const T* ptr)
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{ return (float16x4_t)vld1_s16((const short*)ptr); }
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template <typename T> static inline void vst1_f16(T* ptr, float16x4_t a)
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{ vst1_s16((short*)ptr, a); }
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void cvtScaleHalf_SIMD32f16f( const float* src, size_t sstep, short* dst, size_t dstep, cv::Size size )
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{
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CV_INSTRUMENT_REGION()
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sstep /= sizeof(src[0]);
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dstep /= sizeof(dst[0]);
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|
||||
for( ; size.height--; src += sstep, dst += dstep )
|
||||
{
|
||||
int x = 0;
|
||||
for ( ; x <= size.width - cVectorWidth ; x += cVectorWidth)
|
||||
{
|
||||
float32x4_t v_src = vld1q_f32(src + x);
|
||||
|
||||
float16x4_t v_dst = vcvt_f16_f32(v_src);
|
||||
|
||||
vst1_f16((__fp16*)dst + x, v_dst);
|
||||
}
|
||||
|
||||
for ( ; x < size.width; x++ )
|
||||
{
|
||||
dst[x] = convertFp16SW(src[x]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void cvtScaleHalf_SIMD16f32f( const short* src, size_t sstep, float* dst, size_t dstep, cv::Size size )
|
||||
{
|
||||
CV_INSTRUMENT_REGION()
|
||||
|
||||
sstep /= sizeof(src[0]);
|
||||
dstep /= sizeof(dst[0]);
|
||||
|
||||
for( ; size.height--; src += sstep, dst += dstep )
|
||||
{
|
||||
int x = 0;
|
||||
for ( ; x <= size.width - cVectorWidth ; x += cVectorWidth )
|
||||
{
|
||||
float16x4_t v_src = vld1_f16((__fp16*)src + x);
|
||||
|
||||
float32x4_t v_dst = vcvt_f32_f16(v_src);
|
||||
|
||||
vst1q_f32(dst + x, v_dst);
|
||||
}
|
||||
|
||||
for ( ; x < size.width; x++ )
|
||||
{
|
||||
dst[x] = convertFp16SW(src[x]);
|
||||
}
|
||||
}
|
||||
}
|
||||
#else
|
||||
#error "Unsupported build configuration"
|
||||
#endif
|
||||
}
|
||||
}
|
||||
/* End of file. */
|
173
modules/core/src/convert.hpp
Normal file
173
modules/core/src/convert.hpp
Normal file
@ -0,0 +1,173 @@
|
||||
|
||||
namespace
|
||||
{
|
||||
float convertFp16SW(short fp16);
|
||||
short convertFp16SW(float fp32);
|
||||
|
||||
#if !CV_FP16_TYPE
|
||||
// const numbers for floating points format
|
||||
const unsigned int kShiftSignificand = 13;
|
||||
const unsigned int kMaskFp16Significand = 0x3ff;
|
||||
const unsigned int kBiasFp16Exponent = 15;
|
||||
const unsigned int kBiasFp32Exponent = 127;
|
||||
#endif
|
||||
|
||||
#if CV_FP16_TYPE
|
||||
float convertFp16SW(short fp16)
|
||||
{
|
||||
// Fp16 -> Fp32
|
||||
Cv16suf a;
|
||||
a.i = fp16;
|
||||
return (float)a.h;
|
||||
}
|
||||
#else
|
||||
float convertFp16SW(short fp16)
|
||||
{
|
||||
// Fp16 -> Fp32
|
||||
Cv16suf b;
|
||||
b.i = fp16;
|
||||
int exponent = b.fmt.exponent - kBiasFp16Exponent;
|
||||
int significand = b.fmt.significand;
|
||||
|
||||
Cv32suf a;
|
||||
a.i = 0;
|
||||
a.fmt.sign = b.fmt.sign; // sign bit
|
||||
if( exponent == 16 )
|
||||
{
|
||||
// Inf or NaN
|
||||
a.i = a.i | 0x7F800000;
|
||||
if( significand != 0 )
|
||||
{
|
||||
// NaN
|
||||
#if defined(__x86_64__) || defined(_M_X64)
|
||||
// 64bit
|
||||
a.i = a.i | 0x7FC00000;
|
||||
#endif
|
||||
a.fmt.significand = a.fmt.significand | (significand << kShiftSignificand);
|
||||
}
|
||||
return a.f;
|
||||
}
|
||||
else if ( exponent == -(int)kBiasFp16Exponent )
|
||||
{
|
||||
// subnormal in Fp16
|
||||
if( significand == 0 )
|
||||
{
|
||||
// zero
|
||||
return a.f;
|
||||
}
|
||||
else
|
||||
{
|
||||
int shift = -1;
|
||||
while( ( significand & 0x400 ) == 0 )
|
||||
{
|
||||
significand = significand << 1;
|
||||
shift++;
|
||||
}
|
||||
significand = significand & kMaskFp16Significand;
|
||||
exponent -= shift;
|
||||
}
|
||||
}
|
||||
|
||||
a.fmt.exponent = (exponent+kBiasFp32Exponent);
|
||||
a.fmt.significand = significand << kShiftSignificand;
|
||||
return a.f;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CV_FP16_TYPE
|
||||
short convertFp16SW(float fp32)
|
||||
{
|
||||
// Fp32 -> Fp16
|
||||
Cv16suf a;
|
||||
a.h = (__fp16)fp32;
|
||||
return a.i;
|
||||
}
|
||||
#else
|
||||
short convertFp16SW(float fp32)
|
||||
{
|
||||
// Fp32 -> Fp16
|
||||
Cv32suf a;
|
||||
a.f = fp32;
|
||||
int exponent = a.fmt.exponent - kBiasFp32Exponent;
|
||||
int significand = a.fmt.significand;
|
||||
|
||||
Cv16suf result;
|
||||
result.i = 0;
|
||||
unsigned int absolute = a.i & 0x7fffffff;
|
||||
if( 0x477ff000 <= absolute )
|
||||
{
|
||||
// Inf in Fp16
|
||||
result.i = result.i | 0x7C00;
|
||||
if( exponent == 128 && significand != 0 )
|
||||
{
|
||||
// NaN
|
||||
result.i = (short)( result.i | 0x200 | ( significand >> kShiftSignificand ) );
|
||||
}
|
||||
}
|
||||
else if ( absolute < 0x33000001 )
|
||||
{
|
||||
// too small for fp16
|
||||
result.i = 0;
|
||||
}
|
||||
else if ( absolute < 0x387fe000 )
|
||||
{
|
||||
// subnormal in Fp16
|
||||
int fp16Significand = significand | 0x800000;
|
||||
int bitShift = (-exponent) - 1;
|
||||
fp16Significand = fp16Significand >> bitShift;
|
||||
|
||||
// special cases to round up
|
||||
bitShift = exponent + 24;
|
||||
int threshold = ( ( 0x400000 >> bitShift ) | ( ( ( significand & ( 0x800000 >> bitShift ) ) >> ( 126 - a.fmt.exponent ) ) ^ 1 ) );
|
||||
if( absolute == 0x33c00000 )
|
||||
{
|
||||
result.i = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if( threshold <= ( significand & ( 0xffffff >> ( exponent + 25 ) ) ) )
|
||||
{
|
||||
fp16Significand++;
|
||||
}
|
||||
result.i = (short)fp16Significand;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// usual situation
|
||||
// exponent
|
||||
result.fmt.exponent = ( exponent + kBiasFp16Exponent );
|
||||
|
||||
// significand;
|
||||
short fp16Significand = (short)(significand >> kShiftSignificand);
|
||||
result.fmt.significand = fp16Significand;
|
||||
|
||||
// special cases to round up
|
||||
short lsb10bitsFp32 = (significand & 0x1fff);
|
||||
short threshold = 0x1000 + ( ( fp16Significand & 0x1 ) ? 0 : 1 );
|
||||
if( threshold <= lsb10bitsFp32 )
|
||||
{
|
||||
result.i++;
|
||||
}
|
||||
else if ( fp16Significand == kMaskFp16Significand && exponent == -15)
|
||||
{
|
||||
result.i++;
|
||||
}
|
||||
}
|
||||
|
||||
// sign bit
|
||||
result.fmt.sign = a.fmt.sign;
|
||||
return result.i;
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
namespace cv
|
||||
{
|
||||
namespace opt_FP16
|
||||
{
|
||||
void cvtScaleHalf_SIMD32f16f( const float* src, size_t sstep, short* dst, size_t dstep, cv::Size size );
|
||||
void cvtScaleHalf_SIMD16f32f( const short* src, size_t sstep, float* dst, size_t dstep, cv::Size size );
|
||||
}
|
||||
}
|
@ -135,7 +135,6 @@ typedef void (*BinaryFuncC)(const uchar* src1, size_t step1,
|
||||
uchar* dst, size_t step, int width, int height,
|
||||
void*);
|
||||
|
||||
BinaryFunc getConvertFuncFp16(int ddepth);
|
||||
BinaryFunc getConvertFunc(int sdepth, int ddepth);
|
||||
BinaryFunc getCopyMaskFunc(size_t esz);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user