Replace operators with wrapper functions on universal intrinsics backends #26109
This PR aims to replace the operators(logic, arithmetic, bit) with wrapper functions(v_add, v_eq, v_and...)
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RISC-V/AArch64: disable CPU features detection #25901
This PR is the first step in fixing current issues with NEON/RVV, FP16, BF16 and other CPU features on AArch64 and RISC-V platforms.
On AArch64 and RISC-V platforms we usually have the platform set by default in the toolchain when we compile it or in the cmake toolchain file or in CMAKE_CXX_FLAGS by user. Then, there are two ways to set platform options: a) "-mcpu=<some_cpu>" ; b) "-march=<arch description>" (e.g. "rv64gcv"). Furthermore, there are no similar "levels" of optimizations as for x86_64, instead we have features (RVV, FP16,...) which can be enabled or disabled. So, for example, if a user has "rv64gc" set by the toolchain and we want to enable RVV. Then we need to somehow parse their current feature set and append "v" (vector optimizations) to this string. This task is quite hard and the whole procedure is prone to errors.
I propose to use "CPU_BASELINE=DETECT" by default on AArch64 and RISC-V platforms. And somehow remove other features or make them read-only/detect-only, so that OpenCV wouldn't add any extra "-march" flags to the default configuration. We would rely only on the flags provided by the compiler and cmake toolchain file. We can have some predefined configurations in our cmake toolchain files.
Changes made by this PR:
- `CMakeLists.txt`:
- use `CMAKE_CROSSCOMPILING` instead of `CMAKE_TOOLCHAIN_FILE` to detect cross-compilation. This might be useful in cases of native compilation with a toolchain file
- removed obsolete variables `ENABLE_NEON` and `ENABLE_VFPV3`, the first one have been turned ON by default on AArch64 platform which caused setting `CPU_BASELINE=NEON`
- raise minimum cmake version allowed to 3.7 to allow using `CMAKE_CXX_FLAGS_INIT` in toolchain files
- added separate files with arch flags for native compilation on AArch64 and RISC-V, these files will be used in our toolchain files and in regular cmake
- use `DETECT` as default value for `CPU_BASELINE` also allow `NATIVE`, warn user if other values were used (only for AArch64 and RISC-V)
- for each feature listed in `CPU_DISPATCH` check if corresponding `CPU_${opt}_FLAGS_ON` has been provided, warn user if it is empty (only for AArch64 and RISC-V)
- use `CPU_BASELINE_DISABLE` variable to actually turn off macros responsible for corresponding features even if they are enabled by compiler
- removed Aarch64 feature merge procedure (it didn't support `-mcpu` and built-in `-march`)
- reworked AArch64 and two RISC-V cmake toolchain files (does not affect Android/OSX/iOS/Win):
- use `CMAKE_CXX_FLAGS_INIT` to set compiler flags
- use variables `ENABLE_BF16`, `ENABLE_DOTPROD`, `ENABLE_RVV`, `ENABLE_FP16` to control `-march`
- AArch64: removed other compiler and linker flags
- `-fdata-sections`, `-fsigned-char`, `-Wl,--no-undefined`, `-Wl,--gc-sections` - already set by OpenCV
- `-Wa,--noexecstack`, `-Wl,-z,noexecstack`, `-Wl,-z,relro`, `-Wl,-z,now` - can be enabled by OpenCV via `ENABLE_HARDENING`
- `-Wno-psabi` - this option used to disable some warnings on older ARM platforms, shouldn't harm
- ARM: removed same common flags as for AArch64, but left `-mthumb` and `--fix-cortex-a8`, `-z nocopyreloc`
Update zlib-ng to 2.2.1 #26113
Release: https://github.com/zlib-ng/zlib-ng/releases/tag/2.2.1
ARM diagnostics patch: https://github.com/zlib-ng/zlib-ng/pull/1774
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Add size() to CUDA PtrStepSz #26042
According to [cppreference.com compiler support table](https://en.cppreference.com/w/cpp/compiler_support/17), `nvcc` supports `[[nodiscard]]` from version 11.
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Related: https://github.com/opencv/opencv/pull/25659
Added more data types to OCL flip() and rotate() perf tests #26115
Connected PR with updated sanity data: https://github.com/opencv/opencv_extra/pull/1206
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Avoid uninitialized value read in resize. #26084
When there is no point falling right, an hypothetical value is computed (but unused) using an uninitialized ofst. This triggers warnings in the sanitizers.
Including those values in the for loops is also possible but messy when SIMD is involved.
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Remove the redundant codes of cv::convertMaps and mRGBA2RGBA<uchar> #26071
(1) cv::convertMaps: the branch [else if( m1type == CV_32FC2 && dstm1type == CV_16SC2 ) if( nninterpolate )] is unreachable,
as the condition is satisfied in lines 1959 to 1961, calculated in advance and return directly.
(2) mRGBA2RGBA<uchar>: dst[0], dst[1], dst[2] and dst[3] is calculated repeatedly. Introduced in https://github.com/opencv/opencv/pull/13440
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Update test_tiff.cpp #26093
related #22090
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Added offset for HAL as ofs2idx expects 1-based index #26080
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DNN(ONNX): Enabled several OpenCL conformance tests #26053
The tests also work in 5.x
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Fixed the simd bugs of iPow8u and iPow16u #26061
Add the following cases in opencv_perf_core:
* OCL_PowFixture_iPow.iPow/0, where GetParam() = (640x480, 8UC1)
* OCL_PowFixture_iPow.iPow/2, where GetParam() = (640x480, 16UC1)
iPow8u and iPow16u failed to call to simd accelerating while executing.
Fix the bug by changing the input type of iPow_SIMD function.
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Einsum buffer allocation fix#26059
This PR fixed buffer allocation issue in Einsum layer that causes segmentation fault on 32bit platforms. Related issue #26008
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