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fb8e652c3f
Due to size limit of shared memory, histogram is built on the global memory for CV_16UC1 case. The amount of memory needed for building histogram is: 65536 * 4byte = 256KB and shared memory limit is 48KB typically. Added test cases for CV_16UC1 and various clip limits. Added perf tests for CV_16UC1 on both CPU and CUDA code. There was also a bug in CV_8UC1 case when redistributing "residual" clipped pixels. Adding the test case where clip limit is 5.0 exposes this bug.
222 lines
6.2 KiB
C++
222 lines
6.2 KiB
C++
/*M///////////////////////////////////////////////////////////////////////////////////////
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//
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// IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.
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//
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// By downloading, copying, installing or using the software you agree to this license.
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// If you do not agree to this license, do not download, install,
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// copy or use the software.
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//
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//
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// License Agreement
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// For Open Source Computer Vision Library
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//
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// Copyright (C) 2000-2008, Intel Corporation, all rights reserved.
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// Copyright (C) 2009, Willow Garage Inc., all rights reserved.
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// Third party copyrights are property of their respective owners.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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//
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// * Redistribution's of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// * Redistribution's in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// * The name of the copyright holders may not be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// This software is provided by the copyright holders and contributors "as is" and
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// any express or implied warranties, including, but not limited to, the implied
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// warranties of merchantability and fitness for a particular purpose are disclaimed.
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// In no event shall the Intel Corporation or contributors be liable for any direct,
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// indirect, incidental, special, exemplary, or consequential damages
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// (including, but not limited to, procurement of substitute goods or services;
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// loss of use, data, or profits; or business interruption) however caused
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// and on any theory of liability, whether in contract, strict liability,
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// or tort (including negligence or otherwise) arising in any way out of
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// the use of this software, even if advised of the possibility of such damage.
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//
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//M*/
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#include "perf_precomp.hpp"
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namespace opencv_test { namespace {
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//////////////////////////////////////////////////////////////////////
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// HistEvenC1
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DEF_PARAM_TEST(Sz_Depth, cv::Size, MatDepth);
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PERF_TEST_P(Sz_Depth, HistEvenC1,
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Combine(CUDA_TYPICAL_MAT_SIZES,
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Values(CV_8U, CV_16U, CV_16S)))
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{
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const cv::Size size = GET_PARAM(0);
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const int depth = GET_PARAM(1);
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cv::Mat src(size, depth);
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declare.in(src, WARMUP_RNG);
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if (PERF_RUN_CUDA())
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{
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const cv::cuda::GpuMat d_src(src);
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cv::cuda::GpuMat dst;
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TEST_CYCLE() cv::cuda::histEven(d_src, dst, 30, 0, 180);
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CUDA_SANITY_CHECK(dst);
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}
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else
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{
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const int hbins = 30;
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const float hranges[] = {0.0f, 180.0f};
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const int histSize[] = {hbins};
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const float* ranges[] = {hranges};
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const int channels[] = {0};
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cv::Mat dst;
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TEST_CYCLE() cv::calcHist(&src, 1, channels, cv::Mat(), dst, 1, histSize, ranges);
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CPU_SANITY_CHECK(dst);
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}
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}
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//////////////////////////////////////////////////////////////////////
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// HistEvenC4
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PERF_TEST_P(Sz_Depth, HistEvenC4,
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Combine(CUDA_TYPICAL_MAT_SIZES,
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Values(CV_8U, CV_16U, CV_16S)))
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{
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const cv::Size size = GET_PARAM(0);
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const int depth = GET_PARAM(1);
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cv::Mat src(size, CV_MAKE_TYPE(depth, 4));
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declare.in(src, WARMUP_RNG);
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int histSize[] = {30, 30, 30, 30};
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int lowerLevel[] = {0, 0, 0, 0};
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int upperLevel[] = {180, 180, 180, 180};
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if (PERF_RUN_CUDA())
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{
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const cv::cuda::GpuMat d_src(src);
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cv::cuda::GpuMat d_hist[4];
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TEST_CYCLE() cv::cuda::histEven(d_src, d_hist, histSize, lowerLevel, upperLevel);
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cv::Mat cpu_hist0, cpu_hist1, cpu_hist2, cpu_hist3;
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d_hist[0].download(cpu_hist0);
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d_hist[1].download(cpu_hist1);
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d_hist[2].download(cpu_hist2);
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d_hist[3].download(cpu_hist3);
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SANITY_CHECK(cpu_hist0);
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SANITY_CHECK(cpu_hist1);
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SANITY_CHECK(cpu_hist2);
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SANITY_CHECK(cpu_hist3);
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}
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else
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{
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FAIL_NO_CPU();
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}
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}
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//////////////////////////////////////////////////////////////////////
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// CalcHist
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PERF_TEST_P(Sz, CalcHist,
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CUDA_TYPICAL_MAT_SIZES)
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{
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const cv::Size size = GetParam();
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cv::Mat src(size, CV_8UC1);
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declare.in(src, WARMUP_RNG);
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if (PERF_RUN_CUDA())
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{
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const cv::cuda::GpuMat d_src(src);
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cv::cuda::GpuMat dst;
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TEST_CYCLE() cv::cuda::calcHist(d_src, dst);
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CUDA_SANITY_CHECK(dst);
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}
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else
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{
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FAIL_NO_CPU();
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}
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}
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//////////////////////////////////////////////////////////////////////
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// EqualizeHist
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PERF_TEST_P(Sz, EqualizeHist,
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CUDA_TYPICAL_MAT_SIZES)
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{
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const cv::Size size = GetParam();
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cv::Mat src(size, CV_8UC1);
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declare.in(src, WARMUP_RNG);
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if (PERF_RUN_CUDA())
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{
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const cv::cuda::GpuMat d_src(src);
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cv::cuda::GpuMat dst;
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TEST_CYCLE() cv::cuda::equalizeHist(d_src, dst);
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CUDA_SANITY_CHECK(dst);
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}
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else
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{
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cv::Mat dst;
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TEST_CYCLE() cv::equalizeHist(src, dst);
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CPU_SANITY_CHECK(dst);
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}
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}
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//////////////////////////////////////////////////////////////////////
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// CLAHE
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DEF_PARAM_TEST(Sz_ClipLimit, cv::Size, double, MatType);
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PERF_TEST_P(Sz_ClipLimit, CLAHE,
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Combine(CUDA_TYPICAL_MAT_SIZES,
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Values(0.0, 40.0),
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Values(MatType(CV_8UC1), MatType(CV_16UC1))))
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{
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const cv::Size size = GET_PARAM(0);
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const double clipLimit = GET_PARAM(1);
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const int type = GET_PARAM(2);
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cv::Mat src(size, type);
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declare.in(src, WARMUP_RNG);
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if (PERF_RUN_CUDA())
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{
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cv::Ptr<cv::cuda::CLAHE> clahe = cv::cuda::createCLAHE(clipLimit);
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cv::cuda::GpuMat d_src(src);
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cv::cuda::GpuMat dst;
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TEST_CYCLE() clahe->apply(d_src, dst);
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CUDA_SANITY_CHECK(dst);
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}
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else
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{
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cv::Ptr<cv::CLAHE> clahe = cv::createCLAHE(clipLimit);
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cv::Mat dst;
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TEST_CYCLE() clahe->apply(src, dst);
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CPU_SANITY_CHECK(dst);
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}
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}
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}} // namespace
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