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Update zlib-ng to 2.2.1 #26113 Release: https://github.com/zlib-ng/zlib-ng/releases/tag/2.2.1 ARM diagnostics patch: https://github.com/zlib-ng/zlib-ng/pull/1774 ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [x] The PR is proposed to the proper branch - [ ] There is a reference to the original bug report and related work - [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [ ] The feature is well documented and sample code can be built with the project CMake
216 lines
7.5 KiB
C
216 lines
7.5 KiB
C
/* Copyright (C) 1995-2011, 2016 Mark Adler
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* Copyright (C) 2017 ARM Holdings Inc.
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* Authors:
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* Adenilson Cavalcanti <adenilson.cavalcanti@arm.com>
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* Adam Stylinski <kungfujesus06@gmail.com>
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* For conditions of distribution and use, see copyright notice in zlib.h
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*/
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#ifdef ARM_NEON
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#include "neon_intrins.h"
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#include "zbuild.h"
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#include "adler32_p.h"
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static void NEON_accum32(uint32_t *s, const uint8_t *buf, size_t len) {
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static const uint16_t ALIGNED_(16) taps[64] = {
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64, 63, 62, 61, 60, 59, 58, 57,
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56, 55, 54, 53, 52, 51, 50, 49,
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48, 47, 46, 45, 44, 43, 42, 41,
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40, 39, 38, 37, 36, 35, 34, 33,
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32, 31, 30, 29, 28, 27, 26, 25,
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24, 23, 22, 21, 20, 19, 18, 17,
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16, 15, 14, 13, 12, 11, 10, 9,
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8, 7, 6, 5, 4, 3, 2, 1 };
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uint32x4_t adacc = vdupq_n_u32(0);
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uint32x4_t s2acc = vdupq_n_u32(0);
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uint32x4_t s2acc_0 = vdupq_n_u32(0);
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uint32x4_t s2acc_1 = vdupq_n_u32(0);
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uint32x4_t s2acc_2 = vdupq_n_u32(0);
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adacc = vsetq_lane_u32(s[0], adacc, 0);
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s2acc = vsetq_lane_u32(s[1], s2acc, 0);
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uint32x4_t s3acc = vdupq_n_u32(0);
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uint32x4_t adacc_prev = adacc;
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uint16x8_t s2_0, s2_1, s2_2, s2_3;
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s2_0 = s2_1 = s2_2 = s2_3 = vdupq_n_u16(0);
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uint16x8_t s2_4, s2_5, s2_6, s2_7;
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s2_4 = s2_5 = s2_6 = s2_7 = vdupq_n_u16(0);
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size_t num_iter = len >> 2;
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int rem = len & 3;
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for (size_t i = 0; i < num_iter; ++i) {
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uint8x16x4_t d0_d3 = vld1q_u8_x4(buf);
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/* Unfortunately it doesn't look like there's a direct sum 8 bit to 32
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* bit instruction, we'll have to make due summing to 16 bits first */
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uint16x8x2_t hsum, hsum_fold;
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hsum.val[0] = vpaddlq_u8(d0_d3.val[0]);
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hsum.val[1] = vpaddlq_u8(d0_d3.val[1]);
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hsum_fold.val[0] = vpadalq_u8(hsum.val[0], d0_d3.val[2]);
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hsum_fold.val[1] = vpadalq_u8(hsum.val[1], d0_d3.val[3]);
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adacc = vpadalq_u16(adacc, hsum_fold.val[0]);
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s3acc = vaddq_u32(s3acc, adacc_prev);
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adacc = vpadalq_u16(adacc, hsum_fold.val[1]);
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/* If we do straight widening additions to the 16 bit values, we don't incur
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* the usual penalties of a pairwise add. We can defer the multiplications
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* until the very end. These will not overflow because we are incurring at
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* most 408 loop iterations (NMAX / 64), and a given lane is only going to be
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* summed into once. This means for the maximum input size, the largest value
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* we will see is 255 * 102 = 26010, safely under uint16 max */
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s2_0 = vaddw_u8(s2_0, vget_low_u8(d0_d3.val[0]));
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s2_1 = vaddw_high_u8(s2_1, d0_d3.val[0]);
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s2_2 = vaddw_u8(s2_2, vget_low_u8(d0_d3.val[1]));
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s2_3 = vaddw_high_u8(s2_3, d0_d3.val[1]);
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s2_4 = vaddw_u8(s2_4, vget_low_u8(d0_d3.val[2]));
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s2_5 = vaddw_high_u8(s2_5, d0_d3.val[2]);
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s2_6 = vaddw_u8(s2_6, vget_low_u8(d0_d3.val[3]));
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s2_7 = vaddw_high_u8(s2_7, d0_d3.val[3]);
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adacc_prev = adacc;
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buf += 64;
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}
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s3acc = vshlq_n_u32(s3acc, 6);
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if (rem) {
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uint32x4_t s3acc_0 = vdupq_n_u32(0);
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while (rem--) {
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uint8x16_t d0 = vld1q_u8(buf);
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uint16x8_t adler;
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adler = vpaddlq_u8(d0);
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s2_6 = vaddw_u8(s2_6, vget_low_u8(d0));
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s2_7 = vaddw_high_u8(s2_7, d0);
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adacc = vpadalq_u16(adacc, adler);
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s3acc_0 = vaddq_u32(s3acc_0, adacc_prev);
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adacc_prev = adacc;
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buf += 16;
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}
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s3acc_0 = vshlq_n_u32(s3acc_0, 4);
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s3acc = vaddq_u32(s3acc_0, s3acc);
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}
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uint16x8x4_t t0_t3 = vld1q_u16_x4(taps);
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uint16x8x4_t t4_t7 = vld1q_u16_x4(taps + 32);
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s2acc = vmlal_high_u16(s2acc, t0_t3.val[0], s2_0);
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s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t0_t3.val[0]), vget_low_u16(s2_0));
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s2acc_1 = vmlal_high_u16(s2acc_1, t0_t3.val[1], s2_1);
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s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t0_t3.val[1]), vget_low_u16(s2_1));
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s2acc = vmlal_high_u16(s2acc, t0_t3.val[2], s2_2);
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s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t0_t3.val[2]), vget_low_u16(s2_2));
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s2acc_1 = vmlal_high_u16(s2acc_1, t0_t3.val[3], s2_3);
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s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t0_t3.val[3]), vget_low_u16(s2_3));
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s2acc = vmlal_high_u16(s2acc, t4_t7.val[0], s2_4);
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s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t4_t7.val[0]), vget_low_u16(s2_4));
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s2acc_1 = vmlal_high_u16(s2acc_1, t4_t7.val[1], s2_5);
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s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t4_t7.val[1]), vget_low_u16(s2_5));
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s2acc = vmlal_high_u16(s2acc, t4_t7.val[2], s2_6);
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s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t4_t7.val[2]), vget_low_u16(s2_6));
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s2acc_1 = vmlal_high_u16(s2acc_1, t4_t7.val[3], s2_7);
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s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t4_t7.val[3]), vget_low_u16(s2_7));
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s2acc = vaddq_u32(s2acc_0, s2acc);
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s2acc_2 = vaddq_u32(s2acc_1, s2acc_2);
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s2acc = vaddq_u32(s2acc, s2acc_2);
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uint32x2_t adacc2, s2acc2, as;
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s2acc = vaddq_u32(s2acc, s3acc);
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adacc2 = vpadd_u32(vget_low_u32(adacc), vget_high_u32(adacc));
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s2acc2 = vpadd_u32(vget_low_u32(s2acc), vget_high_u32(s2acc));
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as = vpadd_u32(adacc2, s2acc2);
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s[0] = vget_lane_u32(as, 0);
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s[1] = vget_lane_u32(as, 1);
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}
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static void NEON_handle_tail(uint32_t *pair, const uint8_t *buf, size_t len) {
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unsigned int i;
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for (i = 0; i < len; ++i) {
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pair[0] += buf[i];
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pair[1] += pair[0];
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}
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}
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Z_INTERNAL uint32_t adler32_neon(uint32_t adler, const uint8_t *buf, size_t len) {
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/* split Adler-32 into component sums */
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uint32_t sum2 = (adler >> 16) & 0xffff;
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adler &= 0xffff;
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/* in case user likes doing a byte at a time, keep it fast */
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if (len == 1)
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return adler32_len_1(adler, buf, sum2);
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/* initial Adler-32 value (deferred check for len == 1 speed) */
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if (buf == NULL)
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return 1L;
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/* in case short lengths are provided, keep it somewhat fast */
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if (len < 16)
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return adler32_len_16(adler, buf, len, sum2);
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uint32_t pair[2];
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int n = NMAX;
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unsigned int done = 0;
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/* Split Adler-32 into component sums, it can be supplied by
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* the caller sites (e.g. in a PNG file).
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*/
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pair[0] = adler;
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pair[1] = sum2;
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/* If memory is not SIMD aligned, do scalar sums to an aligned
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* offset, provided that doing so doesn't completely eliminate
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* SIMD operation. Aligned loads are still faster on ARM, even
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* though there's no explicit aligned load instruction */
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unsigned int align_offset = ((uintptr_t)buf & 15);
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unsigned int align_adj = (align_offset) ? 16 - align_offset : 0;
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if (align_offset && len >= (16 + align_adj)) {
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NEON_handle_tail(pair, buf, align_adj);
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n -= align_adj;
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done += align_adj;
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} else {
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/* If here, we failed the len criteria test, it wouldn't be
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* worthwhile to do scalar aligning sums */
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align_adj = 0;
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}
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while (done < len) {
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int remaining = (int)(len - done);
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n = MIN(remaining, (done == align_adj) ? n : NMAX);
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if (n < 16)
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break;
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NEON_accum32(pair, buf + done, n >> 4);
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pair[0] %= BASE;
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pair[1] %= BASE;
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int actual_nsums = (n >> 4) << 4;
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done += actual_nsums;
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}
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/* Handle the tail elements. */
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if (done < len) {
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NEON_handle_tail(pair, (buf + done), len - done);
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pair[0] %= BASE;
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pair[1] %= BASE;
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}
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/* D = B * 65536 + A, see: https://en.wikipedia.org/wiki/Adler-32. */
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return (pair[1] << 16) | pair[0];
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}
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#endif
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