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ba4d6c859d
* added more or less cross-platform (based on POSIX signal() semantics) method to detect various NEON extensions, such as FP16 SIMD arithmetics, BF16 SIMD arithmetics, SIMD dotprod etc. It could be propagated to other instruction sets if necessary. * hopefully fixed compile errors * continue to fix CI * another attempt to fix build on Linux aarch64 * * reverted to the original method to detect special arm neon instructions without signal() * renamed FP16_SIMD & BF16_SIMD to NEON_FP16 and NEON_BF16, respectively * removed extra whitespaces
47 lines
1.2 KiB
C++
47 lines
1.2 KiB
C++
#if defined __GNUC__ && (defined __arm__ || defined __aarch64__)
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#include <stdio.h>
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#include "arm_neon.h"
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/*#if defined __clang__
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#pragma clang attribute push (__attribute__((target("bf16"))), apply_to=function)
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#elif defined GCC
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#pragma GCC push_options
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#pragma GCC target("armv8.2-a", "bf16")
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#endif*/
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bfloat16x8_t vld1q_as_bf16(const float* src)
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{
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float32x4_t s0 = vld1q_f32(src), s1 = vld1q_f32(src + 4);
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return vcombine_bf16(vcvt_bf16_f32(s0), vcvt_bf16_f32(s1));
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}
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void vprintreg(const char* name, const float32x4_t& r)
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{
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float data[4];
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vst1q_f32(data, r);
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printf("%s: (%.2f, %.2f, %.2f, %.2f)\n",
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name, data[0], data[1], data[2], data[3]);
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}
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void test()
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{
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const float src1[] = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f };
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const float src2[] = { 1.f, 3.f, 6.f, 10.f, 15.f, 21.f, 28.f, 36.f };
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bfloat16x8_t s1 = vld1q_as_bf16(src1), s2 = vld1q_as_bf16(src2);
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float32x4_t d = vbfdotq_f32(vdupq_n_f32(0.f), s1, s2);
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vprintreg("(s1[0]*s2[0] + s1[1]*s2[1], ... s1[6]*s2[6] + s1[7]*s2[7])", d);
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}
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/*#if defined __clang__
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#pragma clang attribute pop
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#elif defined GCC
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#pragma GCC pop_options
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#endif*/
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#else
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#error "BF16 is not supported"
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#endif
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int main()
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{
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test();
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return 0;
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}
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