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158 lines
5.4 KiB
Plaintext
158 lines
5.4 KiB
Plaintext
/*M///////////////////////////////////////////////////////////////////////////////////////
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//
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// IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.
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//
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// By downloading, copying, installing or using the software you agree to this license.
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// If you do not agree to this license, do not download, install,
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// copy or use the software.
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//
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//
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// License Agreement
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// For Open Source Computer Vision Library
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//
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// Copyright (C) 2000-2008, Intel Corporation, all rights reserved.
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// Copyright (C) 2009, Willow Garage Inc., all rights reserved.
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// Copyright (C) 1993-2011, NVIDIA Corporation, all rights reserved.
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// Third party copyrights are property of their respective owners.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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//
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// * Redistribution's of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// * Redistribution's in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// * The name of the copyright holders may not be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// This software is provided by the copyright holders and contributors "as is" and
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// any express or bpied warranties, including, but not limited to, the bpied
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// warranties of merchantability and fitness for a particular purpose are disclaimed.
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// In no event shall the Intel Corporation or contributors be liable for any direct,
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// indirect, incidental, special, exemplary, or consequential damages
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// (including, but not limited to, procurement of substitute goods or services;
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// loss of use, data, or profits; or business interruption) however caused
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// and on any theory of liability, whether in contract, strict liability,
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// or tort (including negligence or otherwise) arising in any way out of
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// the use of this software, even if advised of the possibility of such damage.
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//
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//M*/
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#if !defined CUDA_DISABLER
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#include "opencv2/gpu/device/common.hpp"
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#include "opencv2/gpu/device/functional.hpp"
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#include "opencv2/gpu/device/emulation.hpp"
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#include "opencv2/gpu/device/transform.hpp"
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using namespace cv::gpu;
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using namespace cv::gpu::device;
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namespace
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{
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__global__ void histogram256(const uchar* src, int cols, int rows, size_t step, int* hist)
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{
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__shared__ int shist[256];
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const int y = blockIdx.x * blockDim.y + threadIdx.y;
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const int tid = threadIdx.y * blockDim.x + threadIdx.x;
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shist[tid] = 0;
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__syncthreads();
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if (y < rows)
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{
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const unsigned int* rowPtr = (const unsigned int*) (src + y * step);
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const int cols_4 = cols / 4;
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for (int x = threadIdx.x; x < cols_4; x += blockDim.x)
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{
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unsigned int data = rowPtr[x];
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Emulation::smem::atomicAdd(&shist[(data >> 0) & 0xFFU], 1);
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Emulation::smem::atomicAdd(&shist[(data >> 8) & 0xFFU], 1);
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Emulation::smem::atomicAdd(&shist[(data >> 16) & 0xFFU], 1);
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Emulation::smem::atomicAdd(&shist[(data >> 24) & 0xFFU], 1);
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}
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if (cols % 4 != 0 && threadIdx.x == 0)
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{
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for (int x = cols_4 * 4; x < cols; ++x)
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{
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unsigned int data = ((const uchar*)rowPtr)[x];
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Emulation::smem::atomicAdd(&shist[data], 1);
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}
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}
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}
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__syncthreads();
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const int histVal = shist[tid];
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if (histVal > 0)
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::atomicAdd(hist + tid, histVal);
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}
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}
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namespace hist
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{
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void histogram256(PtrStepSzb src, int* hist, cudaStream_t stream)
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{
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const dim3 block(32, 8);
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const dim3 grid(divUp(src.rows, block.y));
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::histogram256<<<grid, block, 0, stream>>>(src.data, src.cols, src.rows, src.step, hist);
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cudaSafeCall( cudaGetLastError() );
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if (stream == 0)
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cudaSafeCall( cudaDeviceSynchronize() );
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}
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}
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/////////////////////////////////////////////////////////////////////////
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namespace
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{
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__constant__ int c_lut[256];
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struct EqualizeHist : unary_function<uchar, uchar>
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{
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float scale;
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__host__ EqualizeHist(float _scale) : scale(_scale) {}
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__device__ __forceinline__ uchar operator ()(uchar val) const
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{
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const int lut = c_lut[val];
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return __float2int_rn(scale * lut);
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}
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};
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}
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namespace cv { namespace gpu { namespace device
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{
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template <> struct TransformFunctorTraits<EqualizeHist> : DefaultTransformFunctorTraits<EqualizeHist>
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{
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enum { smart_shift = 4 };
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};
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}}}
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namespace hist
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{
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void equalizeHist(PtrStepSzb src, PtrStepSzb dst, const int* lut, cudaStream_t stream)
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{
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if (stream == 0)
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cudaSafeCall( cudaMemcpyToSymbol(c_lut, lut, 256 * sizeof(int), 0, cudaMemcpyDeviceToDevice) );
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else
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cudaSafeCall( cudaMemcpyToSymbolAsync(c_lut, lut, 256 * sizeof(int), 0, cudaMemcpyDeviceToDevice, stream) );
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const float scale = 255.0f / (src.cols * src.rows);
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transform(src, dst, EqualizeHist(scale), WithOutMask(), stream);
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}
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}
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#endif /* CUDA_DISABLER */
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